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    Chapter and Conference Paper

    A Hardware Implementation of Word-Parallel Bit-Serial Polynomial Basis Multiplier

    In this paper, a hardware implementation of MSB-first word-parallel bit-serial multiplier with shorter delay time than other existing multipliers in finite field is presented. The proposed multiplier operates ...

    Yong Suk Cho, Jae Yeon Choi in Computer Applications for Graphics, Grid C… (2012)