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Sequential Circuit Technology Map**

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  • First Online:
Encyclopedia of Algorithms

  • 140 Accesses

Years and Authors of Summarized Original Work

  • 1996; Pan, Liu

  • 1998; Pan, Liu

  • 1998; Pan, Lin

Sequential Circuit Technology Map**, Fig. 1
figure 1916 figure 1916

Technology map**: (1) original network, (2) covering, (3) map** solution

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Recommended Reading

  1. Cong J, Ding Y (1994) FlowMap: an optimal technology map** algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans Comput Aided Des Integr Circuits Syst 13(1):1–12

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  2. Cong J, Wu C (1997) FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits. In: ACM/IEEE design automation conference, Anaheim

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  3. Cong J, Wu C, Ding Y (1999) Cut ranking and pruning: enabling a general and efficient FPGA map** solution. In: ACM international symposium on field-programmable gate arrays, Monterey

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  4. Keutzer K (1987) DAGON: technology binding and local optimization by DAG matching. In: ACM/IEEE design automation conference, Miami Beach

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  5. Leiserson CE, Saxe JB (1991) Retiming synchronous circuitry. Algorithmica 6:5–35

    Article  MathSciNet  MATH  Google Scholar 

  6. Mishchenko A, Chatterjee S, Brayton R, Pan P (2006) Integrating logic synthesis, technology map**, and retiming. ERL technical report, EECS Department, UC Berkeley

    Google Scholar 

  7. Pan P (1997) Continuous retiming algorithms and applications. In: IEEE international conference on computer design, Austin

    Google Scholar 

  8. Pan P, Lin CC (1998) A new retiming-based technology map** algorithm for LUT-based FPGAs. In: ACM international symposium on field-programmable gate arrays, Monterey

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  9. Pan P, Liu CL (1996) Optimal clock period FPGA technology map** for sequential circuits. In: ACM/IEEE design automation conference, Las Vegas

    Book  Google Scholar 

  10. Pan P, Liu CL (1998) Optimal clock period FPGA technology map** for sequential circuits. ACM Trans Des Autom Electron Syst 3(3):437–462

    Article  Google Scholar 

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Author information

Authors and Affiliations

  1. **linx, Inc., San Jose, CA, USA

    Peichen Pan

Authors
  1. Peichen Pan
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Corresponding author

Correspondence to Peichen Pan .

Editor information

Editors and Affiliations

  1. Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, USA

    Ming-Yang Kao

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Pan, P. (2016). Sequential Circuit Technology Map**. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2864-4_364

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