Sequential Circuit Technology Map**

1998; Pan, Liu

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Encyclopedia of Algorithms
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Figure 1
figure 1

Technology map**: (1) Original network, (2) covering, (3) map** solution

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Recommended Reading

  1. Cong, J., Ding, Y.: FlowMap: An Optimal Technology Map** Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs. IEEE Trans. on Comput. Aided Des. of Integr. Circuits and Syst., 13(1), 1–12 (1994)

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  2. Cong, J., Wu, C.: FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. ACM/IEEE Design Automation Conference (1997)

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  3. Keutzer, K.: DAGON: Technology Binding and Local Optimization by DAG Matching. ACM/IEEE Design Automation Conference (1987)

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  4. Leiserson, C.E., Saxe, J.B.: Retiming Synchronous Circuitry. Algorithmica 6, 5–35 (1991)

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  5. Mishchenko, A., Chatterjee, S., Brayton, R., Ciesielski, M.: An integrated technology map** environment. International Workshop on Logic Synthesis (2005)

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  6. Pan, P.: Continuous Retiming: Algorithms and Applications. IEEE International Conference on Computer Design, pp. 116–121. (1997)

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  7. Pan, P., Lin, C.C.: A New Retiming-based Technology Map** Algorithm for LUT-based FPGAs. ACM International Symposium on Field-Programmable Gate Arrays (1998)

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  8. Pan, P., Liu, C.L.: Optimal Clock Period FPGA Technology Map** for Sequential Circuits. ACM/IEEE Design Automation Conference, June (1996)

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  9. Pan, P., Liu, C.L.: Optimal Clock Period FPGA Technology Map** for Sequential Circuits. ACM Trans. on Des. Autom. of Electron. Syst., 3(3), 437–462 (1998)

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© 2008 Springer-Verlag

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Pan, P. (2008). Sequential Circuit Technology Map**. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-30162-4_364

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