Abstract
Data transmission is always vulnerable to assault on the digital side. Cipher strength analysis is a crucial component of a business or academic safety evaluation. For data security, a robust encryption process is needed. Therefore, Advanced Encryption Standard (AES), an encoding requirement that was better than the standard, was modified in 2001 by the US National Institute of Standards and Technology. The AES algorithm is solely based on the design of substitution-permutation network concept and performs well in both software and hardware. The described method is an algorithm that uses a single identical secret key for encryption and decryption. Public or private, commercial etc. programmes are not allowed to utilise it. To date, significant research on spot methods is presently being conducted to protect further the AES algorithm. This research work focuses on describing the comparison of time and performance when two FPGAs are utilized for the architecture of the AES. This work introduces a methodology of encrypting AES algorithm for fast processing of IoT devices. In this, the AES algorithm are implemented on two FPGAs and it has been realized that the Spartan-6 FPGA provides better throughput and less time delay to the FPGA based IoT devices.
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Shrivastava, A., Haripriya, D., Borole, Y.D. et al. High performance FPGA based secured hardware model for IoT devices. Int J Syst Assur Eng Manag 13 (Suppl 1), 736–741 (2022). https://doi.org/10.1007/s13198-021-01605-x
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DOI: https://doi.org/10.1007/s13198-021-01605-x