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A Review of Failure Analysis Methods for Advanced 3D Microelectronic Packages

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Abstract

Advanced three dimensional (3D) packaging is a key enabler in driving form factor reduction, performance benefits, and package cost reduction, especially in the fast paced mobility and ultraportable consumer electronics segments. The high level of functional integration and the complex package architecture pose a significant challenge for conventional fault isolation (FI) and failure analysis (FA) methods. Innovative FI/FA tools and techniques are required to tackle the technical and throughput challenges. In this paper, the applications of FI and FA techniques such as Electro Optic Terahertz Pulse Reflectometry, 3D x-ray computed tomography, lock-in thermography, and novel physical sample preparation methods to 3D packages with package on package and stacked die with through silicon via configurations are reviewed, along with the key FI and FA challenges.

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References

  1. Y. Li, Y. Cai, M. Pacheco, R.C. Dias, and D. Goyal, in Proceedings from the 38th International Symposium for Testing and Failure Analysis (ISTFA, ASM International), p. 95 (2012).

  2. R. Agarwal, W. Zhang, P. Limaye, R. Labie, B. Dimcic, A. Phommahaxay, and P. Soussan, in Proceedings of Electronic Components and Technology Conference (ECTC), p. 858 (2010)

  3. Y. Cai, Z. Wang, R.C. Dias, and D. Goyal, in Proceedings from the 36th International Symposium for Testing and Failure Analysis (ISTFA, ASM International), p. 1309 (2010).

  4. D. Smolyansky, Printed Circuit Design, 20 (April 2002).

  5. D. Abessolo-Bidzo, P. Poirier, P. Descamps, and B. Domenges, in Proceedings from the 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), p. 318 (2005).

  6. S.H. Hall, G.W. Hal, and J.A. McCall, High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices (New York: Wiley, 2000).

    Google Scholar 

  7. K. Matsumoto, H. Otsuka, O. Horiuchi, Y.G. Han, W. Choi, and H. Tomokage, Trans. Jpn. Inst. Electron. Packag 6, 57 (2013).

    Article  Google Scholar 

  8. R. Schlangen, S. Motegi, T. Nagatomo, C. Schmidt, F. Altmann, H. Murakami, S. Hollingshead, and J. West, in Proceedings from the 37th International Symposium for Testing and Failure Analysis (ISTFA, ASM International), p. 68 (2011).

  9. F. Naumann, F. Altmann, C. Grosse, and R. Herold, Proceedings from the 40th International Symposium for Testing and Failure Analysis (ISTFA, ASM International), p. 130 (2014).

  10. R. Dias, L. Skoglund, Z. Wang, and D. Smith, in Proceedings from the 27th International Symposium for Testing and Failure Analysis (ISTFA, ASM International), p. 77 (2001).

  11. J. Gaudestad, D. Nuez, and P. Tan, in Proceedings from the 40th International Symposium for Testing and Failure Analysis (ISTFA, ASM International), p. 43 (2014).

  12. A. Orozco, J. Gaudestad, N.E. Gagliolo, C. Rowlett, E. Wong, A. Jeffers, B. Cheng, F.C. Wellstood, A.B. Cawthorne, and F. Infante, in Proceedings from the 39th International Symposium for Testing and Failure Analysis (ISTFA, ASM International), p. 189 (2013).

  13. A. Orozco, N.E. Gagliolo, C. Rowlett, E. Wong, A. Moghe, J. Gaudestad, V. Talanov, A. Jeffers, K. Torkashvan, F.C. Wellstood, S. Dobritz, M. Boettcher, A.B. Cawthorne, and F. Infante, in Proceedings from the 40th International Symposium for Testing and Failure Analysis (ISTFA, ASM International), p. 33 (2014).

  14. Y. Li, J.S. Moore, B. Pathangey, R.C. Dias, and D. Goyal, IEEE Trans. Device Mater. Reliab. 12, 494 (2012).

    Article  Google Scholar 

  15. M. Pacheco and D. Goyal, in Proceedings of Electronic Components and Technology Conference, p. 1263 (2011).

  16. Y. Li, M. Pacheco, D. Goyal, J. W. Elmer, H.D. Barth, and D. Parkinson, in Conference Proceedings from the 64th Electronic Components and Technology Conference (ECTC), p. 1457 (2014).

  17. J.W. Elmer, Y. Li, H.D. Barth, D.Y. Parkinson, M. Pacheco, and D. Goyal, J. Electron. Mater. 43, 4421 (2014).

    Article  Google Scholar 

  18. F. Altmann, J. Beyersdorfer, J. Schischka, M. Krause, G. Franz, and L. Kwakman, in Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis (ISTFA, ASM International), p. 39 (2012).

  19. L. Kwakman, M. Straw, G. Coustillier, M. Sentis, J. Beyersdorfer, J. Schischka, F. Naumann, and F. Altmann, in Proceedings from the 38th International Symposium for Testing and Failure Analysis (ISTFA, ASM International), p. 17 (2013).

  20. A. Meyer, G. Grimm, M. Hecker, M. Weisheit, and E. Langer, in Proceedings from the 38th International Symposium for Testing and Failure Analysis (ISTFA, ASM International), p. 12 (2013).

  21. M.H. Lu, D.Y. Shih, P. Lauro, C. Goldsmith, and D.W. Henderson, Appl. Phys. Lett. 92, 211909 (2008).

    Article  Google Scholar 

  22. Y. Wang and P.S. Ho, Appl. Phys. Lett. 103, 121909 (2013).

    Article  Google Scholar 

  23. P. Liu, A. Overson, and D. Goyal, in Conference Proceedings from the 65th Electronic Components and Technology Conference (ECTC), p. 99 (2015).

  24. C. Wu, T. Jiang, J. Im, K.M. Liechti, R. Huang, and P.S. Ho, in Proceedings from the 21st International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), p. 312 (2014).

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Authors and Affiliations

  1. Assembly Test and Technology Development Failure Analysis Labs, Intel Corporation, 5000 W. Chandler BLVD., Chandler, AZ, 85226, USA

    Yan Li, Purushotham Kaushik Muthur Srinath & Deepak Goyal

Authors
  1. Yan Li
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  2. Purushotham Kaushik Muthur Srinath
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  3. Deepak Goyal
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Correspondence to Yan Li.

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Li, Y., Srinath, P.K.M. & Goyal, D. A Review of Failure Analysis Methods for Advanced 3D Microelectronic Packages. J. Electron. Mater. 45, 116–124 (2016). https://doi.org/10.1007/s11664-015-4165-y

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  • DOI: https://doi.org/10.1007/s11664-015-4165-y

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