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Scalability analysis of AVX-512 extensions

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Abstract

Energy efficiency below a specific thermal design power (TDP) has become the main design goal for microprocessors across all market segments. Optimizing the usage of the available transistors within the TDP is a pending topic. Parallelism is the basic foundation for achieving the exascale level. While instruction-level and thread-level parallelism are embraced by developers, data-level parallelism is usually underutilized, despite its huge potential (e.g. single-instruction multiple-data execution). Companies are pushing the size of vector registers to double every 4 years. Intel’s AVX-512 (512-bit registers) and ARM’s SVE (up to 2048-bit registers) are examples of such trend. In this paper, we perform a scalability and energy efficiency analysis of AVX-512 using the ParVec benchmark suite. ParVec is extended to add support for AVX-512 as well as the newest versions of the GCC compiler . We use Intel’s Top–Down model to show the main bottlenecks of the architecture for each studied benchmark. Results show that the performance and energy improvements depend greatly on the fraction of code that can be vectorized . Energy improvements over scalar codes in a single-thread environment range from 2\(\times \) for Streamcluster (worst) to 8\(\times \) for Blackscholes (best).

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Notes

  1. Micro-operations.

  2. Set of macros used to generate the intrinsics code using the C pre-processor.

  3. Model Specific Registers.

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Authors and Affiliations

  1. University of Murcia, Murcia, Spain

    Juan M. Cebrian

  2. Norwegian University of Science and Technology (NTNU), Trondheim, Norway

    Lasse Natvig & Magnus Jahre

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  1. Juan M. Cebrian
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  2. Lasse Natvig
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  3. Magnus Jahre
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Correspondence to Juan M. Cebrian.

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Cebrian, J.M., Natvig, L. & Jahre, M. Scalability analysis of AVX-512 extensions. J Supercomput 76, 2082–2097 (2020). https://doi.org/10.1007/s11227-019-02840-7

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