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A highly linear CMOS transconductance amplifier in 180 nm process technology

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Abstract

The present article describes the design and analysis of an operational transconductance amplifier (voltage to current converter) with wide linear input range. The proposed configuration combines the techniques of signal attenuation and source degeneration in order to reduce the odd order harmonic distortion significantly. The proposed circuit is compared with several circuit topologies based on MOS differential pairs with respect to their achievable linearity, input referred noise and power consumption. The linear transconductor is designed and simulated in 180 nm CMOS process technology with 1.8 V power supply. Simulation results show third order harmonic distortion (HD 3) of −70 dB for 600 mVpp input signal. For 1% transconductance variation the linear range is about 1.2 Vpp. The input referred noise of the transconductor is \(70\,\hbox{nV}/\sqrt{\text {Hz}}\) at 10 MHz. The quiescent power consumption is only 450 μW.

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Acknowledgements

Authors would like to thank Mr. Vivek Goyal for his help in the formulation of the problem in the initial phase of this study.

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  1. Department of Electrical Engineering, Indian Institute of Technology, Kharagpur, India

    Sougata Kumar Kar & Siddhartha Sen

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  1. Sougata Kumar Kar
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  2. Siddhartha Sen
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Correspondence to Sougata Kumar Kar.

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Kar, S.K., Sen, S. A highly linear CMOS transconductance amplifier in 180 nm process technology. Analog Integr Circ Sig Process 72, 163–171 (2012). https://doi.org/10.1007/s10470-011-9796-1

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  • DOI: https://doi.org/10.1007/s10470-011-9796-1

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