Abstract
This paper presents a CORDIC-based radix-4 FFT processor, which adopts an improved conflict-free parallel memory access scheme and the pipelined CORDIC architecture. By generating the twiddle factor correctly, the proposed FFT processor eliminates the need of ROM making it memory-efficient. Synthesis results show that the 16-bit 1024-point FFT processor only has 45 K equivalent gates with area of 0.13 mm2 excluding memories in Chartered 90 nm CMOS technology. When the operating frequency is 350 MHz, the proposed FFT processor performs 1024-point FFT every 3.94 μs.
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Acknowledgments
The authors would like to thank the National Natural Science Foundation Council and the Key Specific Project of China, to financially support this work under Grants No. 60970037 and No. 2009ZX01034-001-001-006.
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Liu, D., Liu, H., Zhang, J., Zhang, B., Zhou, L. (2012). VLSI Design of a Hardware Efficient FFT Processor. In: J. (Jong Hyuk) Park, J., Leung, V., Wang, CL., Shon, T. (eds) Future Information Technology, Application, and Service. Lecture Notes in Electrical Engineering, vol 164. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-4516-2_7
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DOI: https://doi.org/10.1007/978-94-007-4516-2_7
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