Abstract
Rate distortion optimization (RDO) technique is the best known mode decision method in recent video coding standard, such as H.264 and AVS. However, the unbearable computational burden limits its application. According to the proposed block-level pipeline architecture of RDO-based MD, we find that zigzag scanning and entropy coding are the bottlenecks. In our paper, we firstly analyze the time consumption of the bottlenecks, and then we propose our efficient zigzag scanning and entropy coding architecture. Finally, our enhanced architecture is implemented in AVS encoder. The experimental results show that 20% throughput can be increased compared with the 4-way parallel scanning and entropy coding. With the proposed architecture, the real time RDO-based MD processing of 1080P@30fps can be supported. And our design is realized in high-level Verilog/VHDL hardware description language and implemented under SMIC 0.18μm CMOS technology with 50K logic gates and 6 KB SRAMs at 237MHZ operation frequency.
This work is partially supported by grants from the Chinese National Natural Science Foundation under contract No.61171139 and No. 61035001, and National High Technology Research and Development Program of China (863 Program) under contract No.2012AA011703.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Zhang, T., Li, S., Tian, G., Ikenaga, T., Goto, S.: High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. In: International Conference on Communications, Circuits and Systems, ICCCAS (May 2008)
Wang, Q., Zhao, D., Gao, W., Ma, S.: Low complexity RDO mode decision based on a fast coding-bits estimation model for H.264/AVC. In: IEEE International Symposium on Circuits and Systems, ISCAS 2005 (May 2005)
Pan, F., Lin, X., Susanto, R., Lim, K.P., Li, Z.G., Feng, G.N., Wu, D.J., Wu, S.: Fast mode decision algorithm for intraprediction in H.264/AVC video coding. IEEE Trans. Circuits Syst. Video Technol. 15(7), 813–822 (2005)
Yin, H., Wang, X., Zhu, X., Qi, H.: Hardware Friendly Mode Decision Algorithm for High Definition AVS Video Encoder. In: 2nd International Congress on Image and Signal Processing, CISP 2009 (October 2009)
Wang, X., Zhu, C., Yin, H., Gao, W., **e, X., Jia, H.: Fast Mode Decision Based on RDO for AVS High Definition Video Encoder. In: Qiu, G., Lam, K.M., Kiya, H., Xue, X.-Y., Kuo, C.-C.J., Lew, M.S. (eds.) PCM 2010, Part II. LNCS, vol. 6298, pp. 62–72. Springer, Heidelberg (2010)
An, D., Tong, X., Zhu, B., He, Y.: A novel fast DCT coefficient scan architecture. In: Picture Coding Symposium, pp. 1–4 (2009)
Huang, Y.-W., Hsieh, B.-Y., Chen, T.-C., Chen, L.-G.: Hardware Architecture Design for H.264/AVC Intra Frame Coder. In: Proceedings of ISCAS 2004, May 23-26, vol. 2, pp. II-269–II-272 (2004)
Yang, W., Yin, H., Gao, W., Qi, H., **e, X.: Multi-stage motion vector prediction schedule strategy for AVS HD encoder. In: 2010 Digest of Technical Papers International Conference on Consumer Electronics, ICCE (January 2010)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer International Publishing Switzerland
About this paper
Cite this paper
Cui, T. et al. (2013). An Efficient Zigzag Scanning and Entropy Coding Architecture Design. In: Huet, B., Ngo, CW., Tang, J., Zhou, ZH., Hauptmann, A.G., Yan, S. (eds) Advances in Multimedia Information Processing – PCM 2013. PCM 2013. Lecture Notes in Computer Science, vol 8294. Springer, Cham. https://doi.org/10.1007/978-3-319-03731-8_33
Download citation
DOI: https://doi.org/10.1007/978-3-319-03731-8_33
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-03730-1
Online ISBN: 978-3-319-03731-8
eBook Packages: Computer ScienceComputer Science (R0)