Abstract
RISC-V has been favored by major research institutions and universities since its emergence. However, there is a lack of relevant information on the research of general-purpose operating systems based on the RISC-V ISA, and the specialized nature of the available information has become an important obstacle to its entry into academic research and teaching. To address the aforementioned issues and further promote the adoption of RISC-V in university education and research, we design a RISC-V operating system based on the C language, called Moonix. It is divided into four modules: interrupt management, memory management, thread scheduling, and file system. Moonix can not only run on QEMU but also on the Nezha D1-H development board. Students can run Moonix on a real hardware, which can further stimulate their interest in learning operating systems.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Allwinner Technology Co., L: D1-H User Manual Version 1.0 (2022)
Asanović, K., Patterson, D.A.: Instruction sets should be free: The case for risc-v. EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2014-146 (2014)
Blem, E., Menon, J., Sankaralingam, K.: Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures. In: 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), pp. 1–12 (2013). https://doi.org/10.1109/HPCA.2013.6522302
Di Mascio, S., Menicucci, A., Furano, G., Monteleone, C., Ottavi, M.: The case for RISC-V in space. In: Saponara, S., De Gloria, A. (eds.) ApplePies 2018. LNEE, vol. 573, pp. 319–325. Springer, Cham (2019). https://doi.org/10.1007/978-3-030-11973-7_37
Flamand, E., et al.: GAP-8: A RISC-V SoC for AI at the Edge of the IoT. In: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 1–4 (2018). https://doi.org/10.1109/ASAP.2018.8445101
Greengard, S.: Will RISC-V revolutionize computing? Commun. ACM 63(5), 30–32 (2020). https://doi.org/10.1145/3386377
Jiang, J.: XFEL: Tiny FEL tools for allwinner SOC. https://github.com/xboot/xfel
Kanter, D.: RISC-V Offers Simple. Modular ISA. Tech. rep, The Linley Group (2016)
Keller, B., et al.: A RISC-V processor SoC With integrated power management at submicrosecond timescales in 28 nm FD-SOI. IEEE J. Solid-State Circ. 52(7), 1863–1875 (2017). https://doi.org/10.1109/JSSC.2017.2690859
Lee, Y., et al.: An agile approach to building RISC-V microprocessors. IEEE Micro 36(2), 8–20 (2016). https://doi.org/10.1109/MM.2016.11
Matthews, E., Shannon, L.: TAIGA: a new RISC-V soft-processor framework enabling high performance CPU architectural features. In: 2017 27th International Conference on Field Programmable Logic and Applications (FPL), pp. 1–4 (2017). https://doi.org/10.23919/FPL.2017.8056766
Rasmussen, R.V., Trick, M.A.: Round robin scheduling - a survey. Eur. J. Oper. Res. 188(3), 617–636 (2008). https://doi.org/10.1016/j.ejor.2007.05.046
Waterman, A., Lee, Y., Patterson, D.A., Asanovi, K.: The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0. Tech. rep. (2014)
Waterman, A., Lee, Y., Patterson, D.A., Asanovi, K.: The RISC-V Instruction Set Manual Volume 2: Privileged Architecture Version 1.7. Tech. rep. (2015)
Western Digital Corporation or its affiliates: RISC-V Open Source Supervisor Binary Interface (OpenSBI). https://github.com/riscv-software-src/opensbi
Acknowledgements
This work is supported by the National Natural Science Foundation of China (61976071), and the Natural Science Foundation of Heilongjiang Province of China (LH2020F012).
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2024 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Liu, G., Li, E., Huang, J., Guo, Z. (2024). Moonix: An Educational Operating System on Nezha D1-H RISC-V Development Board. In: Gan, J., Pan, Y., Zhou, J., Liu, D., Song, X., Lu, Z. (eds) Computer Science and Educational Informatization. CSEI 2023. Communications in Computer and Information Science, vol 1900. Springer, Singapore. https://doi.org/10.1007/978-981-99-9492-2_2
Download citation
DOI: https://doi.org/10.1007/978-981-99-9492-2_2
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-99-9491-5
Online ISBN: 978-981-99-9492-2
eBook Packages: Computer ScienceComputer Science (R0)