Abstract
Gardon Moore proposed the exponential increase in transistor packing density on integrated circuits (ICs). The semiconductor industry has managed to keep up with this exponential expansion of transistors over the last few decades. However, aggressive downscaling of devices is necessary to meet technological demands to reduce power consumption, cost, and increase the speed of complementary metal oxide semiconductor (CMOS) devices. These CMOS devices face serious short-channel effects like drain-induced barrier lower, drain punch through, hot carrier effect, and mobility degradation. Apart from this, the subthreshold swing of MOS crosses the fundamental limit of device operation, making it unfavorable while scaling from the micrometer to the nanometer region. Another MOSFET constraint brought on by a reduction in gate oxide thickness is improved by using high-k dielectric material in the gate stack structure and SiO2 as an interfacial layer to reduce leakage current. To overcome all these limitations, tunnel field-effect transistor (TFET) is taken into account. TFET offers low IOFF, and its subthreshold swing is below 60 mV/dec.
This chapter focuses on physics-based simulation and modeling of heterojunction TFETs with various gate topologies. A combination of SiO2 and high permittivity dielectric material is used as the gate oxide stack. The first part of the chapter focuses on the analytical modeling of a dual-material asymmetric hetero-dielectric gate tunnel field-effect transistor (FET), which is carried out based on the Poisson equation and parabolic approximation techniques. An asymmetric gate with two materials having different work functions is used to increase the ON current of the device. The lengths of metal one and metal two are taken to be 10 nm and 10 nm, respectively, and the device performance is analyzed. Expressions for the surface potential, electric field, and drain current are obtained by using a two-dimensional (2D) mathematical model, whose results are compared with those obtained using the Silvaco technology computer-aided design (TCAD) simulator, revealing good agreement. The proposed dual-material asymmetric gate tunnel FET produces an improved ON current of 10−5 A/μm and a decreased OFF current of 10−10 A/μm, with an ON/OFF ratio of 105.
The influence of trap carriers at the Si-SiO2 interface near the source channel junction is analyzed in the second part of the chapter. The device’s performance is analyzed by considering the depletion regions of the p-i-n structure. The analytical model of the proposed device is carried out with appropriate boundary conditions, and the Poisson equation is solved by using the parabolic approximation technique. Surface potential, electric field, and drain current are computed using the developed model. This work considers the device’s four lengths (L1, L2, L3, and L4) for the source, channel, and drain regions. This work employs two metal work functions (M1 and M2) placed over HfO2 and SiO2. The drain current is computed using the analytical model for SiO2/HfO2 cylindrical gate tunnel FET. An ON current of 10−5 A/μm and OFF current of 10−19 A/μm, with an ON/OFF ratio of 1014 is produced in the proposed device.
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Anand, I.V., Samuel, T.S.A. (2024). Modeling and Simulation of Dual-Material Asymmetric Heterojunction Tunnel Field-Effect Transistors. In: Song, Y.S., Thoutam, L.R., Tayal, S., Rahi, S.B., Samuel, T.S.A. (eds) Handbook of Emerging Materials for Semiconductor Industry. Springer, Singapore. https://doi.org/10.1007/978-981-99-6649-3_24
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DOI: https://doi.org/10.1007/978-981-99-6649-3_24
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