Designing of Ternary to Binary Half Adder Using CMOS

Abstract

Digital systems are designed using binary radix which works on two-valued logic popularly known as low (0) and high (1). The logic operations are performed using underlying transistor switching actions. However, further reduction in minimum feature size of the transistors implementing binary-based digital systems is severely challenged by heat dissipation among other issues. To further improve the packing density, researchers are looking for higher radix number system over aggressive device scaling. Higher radix system is capable of reducing the number of wire interconnects. Ternary logic provides a good alternative to existing binary system logic in terms of reduced interconnects and higher operating speeds. Ternary logic devices are expected to offer a significant increase in information handling capability over binary logic systems. The present paper proposes a circuit for ternary to binary half adder using CMOS technology. The circuit for ternary decoder, ternary logic gates (TNOR, TAND, TOR), ternary inverters (STI, PTI, NTI), and T-buffer are also designed. The proposed design has been simulated using the CADENCE tool with 90 nm CMOS technology. The proposed ternary to binary adder circuit can be used as basic building block for different logic functions, and other important derived circuits like ternary memory, multiplier, and multiplexer. The proposed design of the ternary adder achieves lower power dissipation and improved power delay product. Furthermore, the results show the potential advantage of these half adders in complex arithmetic circuits for implementing the microprocessor and controllers.