Abstract
The Tunnel field-effect transistors (TFETs) leverage quantum tunneling for efficient power consumption and improved switching capabilities. In this paper, we have demonstrated the impact of parametric variation on electrostatics and analog performance of the proposed tunnel field-effect transistor (ESDGTFET) device using Silvaco 2D device simulator. The paper investigates various parameters like threshold voltage, ION/IOFF ratio, drain current, subthreshold swing (SS), transconductance(gm) and cutoff frequency (fT) for different channel lengths and gate dielectric materials. The finding from the investigation reveals that the subthreshold swing (SS) is improved by 49% when the channel length is reduced from 40 to 20nm but no notable changes were observed in threshold voltage. The total capacitance of the device is also improved for a shorter channel length. Furthermore, the on current and SS of the device are improved for HfO2 gate dielectric material as compared to SiO2. For high-k dielectrics, the device’s threshold voltage drops substantially. As a result, the device functions optimally in low-power contexts.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Wong HSP, Frank DJ, Solomon PM, Wann CHJ, Welser JJ (1999) Nanoscale CMOS. Proc IEEE 87:537–570
Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy efficient electronic switches. Nat Nanotechnol 479:329–337
Huang JST, Schrankler JW (1987) Switching characteristics of scaled CMOS circuits at 77 K. IEEE Trans Electron Devices 34(1):101–106
Kuhn K (2018) CMOS and beyond CMOS: scaling challenges. In High mobility materials for CMOS applications, pp. 1–44, Woodhead Publishing
Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy efficient electronic switches. Nature 479(7373):329–337
Wang PF (2004) Complementary tunneling transistor for low power application. Solid-State Electron 48:2281–2286
Choi WY, Park BG, Lee JD, Liu TJK (2007) Tunneling field effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett 28(8):743–745
Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans Electron Devices 54(7):1725–1733
Seabaugh AC, Zhang Q (2010) Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE 98(12):2095–2110
Datta S, Liu H, Narayanan V (2014) Tunnel FET technology: a reliability perspective. Microelectron Reliab 54(5):861–874
Wu J, Min J, Taur Y (2015) Short-channel effects in tunnel FETs. IEEE Trans Electron Devices 62(9):3019–3024
Kavalieros J, Doyle B, Datta S, Dewey G, Doczy M, ** B, Lionberger D, Metz M, Rachmady W, Radosavljevic M, Shah U, Zelick N, Chau R (2006) Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering. VLSI Tech Digest, 50–51
Dubey PK, Kaushik BK (2017) T-shaped III-V heterojunction tunnelling field-effect transistor. IEEE Trans Electron Devices 64(8):3120–3125
Kim SW, Choi WY (2016) Hump effects of germanium/silicon heterojunction tunnel field-effect transistors. IEEE Trans Electron Devices 63(6):2583–2588
Raad BR, Nigam K, Sharma D, Kondekar PN (2016) Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement. Superlattices Microstruct 94:138–146
Nirmal D, Nalini B, Vijaya P (2010) Nanosized high κ dielectric material for FINFET. Integr Ferroelectr 121(1):31–35
Narang R, Saxena M, Gupta RS, Gupta M (2013) Device and circuit level performance comparison of tunnel FET architectures and impact of heterogeneous gate dielectric. J of Semiconductor Technol Sci 13:224–236
Dutta U, Soni MK, Pattanaik M (2019) Simulation study of hetero dielectric tri material gate tunnel FET based common source amplifier circuit. AEU- Int J Electron Commun 99:258–263
ATLAS Device Simulation Software, Silvaco Int., Santa. Clara, CA, Version 5.14.0.R, 2013
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2024 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Vedvrat, Gupta, V., Tripathi, R. (2024). Design and Parametric Variation Assessment of Extended Source Double Gate Tunnel Field-Effect Transistor (ESDGTFET) for Enhanced Performance. In: Marriwala, N.K., Dhingra, S., Jain, S., Kumar, D. (eds) Mobile Radio Communications and 5G Networks. MRCN 2023. Lecture Notes in Networks and Systems, vol 915. Springer, Singapore. https://doi.org/10.1007/978-981-97-0700-3_24
Download citation
DOI: https://doi.org/10.1007/978-981-97-0700-3_24
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-97-0699-0
Online ISBN: 978-981-97-0700-3
eBook Packages: EngineeringEngineering (R0)