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Fault-Tolerant Circuits

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Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design

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Abstract

With the scaling of semiconductor process technology, the performance of modern VLSI chips improves significantly. However, the aggressive technology scaling poses serious challenges to lifetime reliability. Two of the paramount challenges are soft errors and aging-driven lifetime reliability. Although many studies have been done to tackle the two challenges, most take them separately so far, thereby failing to reach better performance-cost trade-offs. To achieve an optimum performance-cost trade-off, we propose a unified fault detection scheme—stability violation-based fault detection (SVFD). Besides, since the performance of modern VLSI chips improves significant, the on-chip path delay measurement techniques have been gained many attentions for researchers in recent years, for it can provide a cost-effective alternative way to perform delay defect detection and silicon debug in modern VLSI chips. Furthermore, to help to reduce hardware overheads and delay measurement time for on-chip path delay measurement, we propose a novel on-chip path delay measurement architecture, OCDM, for path delay testing and silicon debug. Since paramount challenges come from a variety of aging mechanisms that can cause gradual performance degradation of circuits. Prior work shows that such progressive degradation can be reliably detected by dedicated aging sensors, which provides a good foundation for proposing a new scheme to improve lifetime reliability. Based on our previous researches, we further propose ReviveNet, a hardware-implemented aging-aware and self-adaptive architecture. Aging awareness is realized by deploying dedicated aging sensors, and self-adaptation is achieved by employing a group of synergistic agents. Each agent implements a localized timing adaptation mechanism to tolerate aging-induced delay on critical paths.

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Authors and Affiliations

  1. State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Bei**g, China

    **aowei Li

  2. State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Bei**g, China

    Guihai Yan

  3. State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Bei**g, China

    Cheng Liu

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Li, X., Yan, G., Liu, C. (2023). Fault-Tolerant Circuits. In: Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design. Springer, Singapore. https://doi.org/10.1007/978-981-19-8551-5_2

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