Abstract
Here in this scope we have proposed a noble adiabatic dynamic CMOS logic circuit known as two phase adiabatic dynamic logic. The proposed two 2 phase ADCL uses two complementary sinusoidal power supply clocks known as power clock. As a result, the propagation delay of the 2PADCL is smaller than that of the conventional ADCL circuits and conventional CMOS circuits. The simulation results also show that the power dissipation of the 2PADCL circuit is lower than those of other conventional adiabatic logic circuits and conventional CMOS circuits. The adiabatic performance parameter which is known as energy saving factor is also estimated in lower and higher frequency ranges. We have also estimated the power delay product of ADCL and proposed 2PADCL logic.
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Samanta, S., Mahapatra, R., Mal, A.K. (2023). Analysis of 2PADCL Energy Recovery Logic for Ultra Low Power VLSI Design for SOC and Embedded Applications. In: Gyei-Kark, P., Jana, D.K., Panja, P., Abd Wahab, M.H. (eds) Engineering Mathematics and Computing. Studies in Computational Intelligence, vol 1042. Springer, Singapore. https://doi.org/10.1007/978-981-19-2300-5_18
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DOI: https://doi.org/10.1007/978-981-19-2300-5_18
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