Abstract
Video compression and decompression are an inevitable part of the multimedia applications. There is a need for effective algorithms that can reduce the bandwidth along with maintaining the perceptual quality of the images. H.264 is a video coding standard by ITU/T and ISO/IEC groups that fits the purpose. Design of H.264 decoder as an IP is developed using xilinx ISE design suite. Functional verification of the same is carried out in ISE simulator. The physical design of the decoder is carried out using OpenLANE synthesis and PR software using sky130nm PDK. The IP core dimensions are 148.57 mm length and 146.88 mm width. The end IP meets the timing constraints and is free from DRC and LVS errors.
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Revanoor, G., Prabhavathi, P. (2022). Design and Verification of H.264 Advanced Video Decoder. In: Raj, J.S., Kamel, K., Lafata, P. (eds) Innovative Data Communication Technologies and Application. Lecture Notes on Data Engineering and Communications Technologies, vol 96. Springer, Singapore. https://doi.org/10.1007/978-981-16-7167-8_38
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DOI: https://doi.org/10.1007/978-981-16-7167-8_38
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