Abstract
There are various advanced video-displaying instruments which are responsible for producing high-resolution video data. Due to damaged disk like DVD or other media player, there is huge probability of distortion occur in reproduced video data. Error concealment technique is at decoder side, which has been developed to recover the damaged or lost region by utilizing temporal/spatial redundant information using intra/inter-mode prediction. This phase of intra-prediction mode decision in H.264/AVC intra-frame coder consumes more time with high computational complexity due to iterative process of prediction. Now, for real-time application the novel VLSI architecture for intra-prediction was developed which reduces redundancy and high number of memory access. This proposed architecture is implemented for all nine modes, and novel architecture is processing for 4 × 4 as well as 16 × 16 block size for intra-prediction modes. The proposed hardware design is implemented in VHDL with target device vitex6 (xc6vlx75t-3ff484). This proposed method provides rearrangement of intra-prediction equations, which reduced computational complexity by reducing gate count, and also minimizes iterative process by 29 clock cycle for one macroblock retrieval. Compared to state of the art, the proposed architecture reduces computational complexity.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Richardson IE (2010) The H.264 advanced video compression standard, 2nd edn. Vocodex Limited, Willey
Orlandic M, Svarstad K (2013) A high-throughput and low-complexity H. 264/AVC intra 16 × 16 prediction architecture for HD video sequences. In: 2013 21st Telecommunications forum (TELFOR). IEEE, pp 529–532
Xu K, Choy CS (2008) A power-efficient and self-adaptive prediction engine for H. 264/AVC decoding. IEEE Trans Very Large Scale Integr (VLSI) Syst 16(3):302–313
Nadeem M, Wong S, Kuzmanov G (2011) An efficient hardware design for intra-prediction in h. 264/AVC decoder. In: Electronics, Communications and Photonics Conference (SIECPC), 2011 Saudi International. IEEE, pp 1–6
Atitallah AB, Loukil H, Masmoudi N (2011) Fpga design for H. 264/avc encoder. Int J Comput Sci Eng Appl 1(5)
Hsia S, Hsu W, Chou Y (2012) Fast low-complexity computation and real-time architecture for h.264/avc intra-prediction. J Real time Image Process
Atitallah AB, Loukil H, Masmoudi N (2011) FPGA design for h. 264/avc encoder. Int J Comput Sci Eng Appl 1(5):119
Meng B, Au OC, Wong C-W, Lam H-K (2003) Efficient intra-prediction mode selection for 4 × 4 Blocks in H.264. In: IEEE conference on multimedia and expo, vol 3, pp III-521–4
Shafique M, Bauer L, Henkel J (2009) A parallel approach for high performance hardware design of intra prediction in H. 264/AVC video codec. In: Proceedings of the conference on design, automation and test in Europe. European Design and Automation Association, pp 1434–1439
Wang X, Cui X, Yu D (2009) A parallel intra prediction architecture for H.264 video decoding. In: IEEE international conference on ASIC, pp 859–862
Chiang K-C, Wu MF, J.J.-J. Shann, Modification and implementation of an edge-based fast intra prediction mode decision algorithm for H.264/AVC high resolution real-time systems. J Visual Commun Image Representation 23(2), 245–253 (ISSN 1047-3203)
Shrivastava VK, Muralidhar P, Rama Rao CB (2013) Architecture for H.264 intra prediction fast mode decision algorithm. Int J Comput Appl 68(3):0975–8887
Kannangara CS, Richardson IEG, Bystrom M, Zhao Y, Solera J, MacLennan A, Cooney R (2006) Low complexity skip prediction for H.264 through lagrangian cost estimation. IEEE Trans Circ Syst Video Technol 16(2):202–208
Kim D-Y, Han K-H, Lee Y-L (2010) Adaptive single-multiple prediction for H.264/AVC intra coding. IEEE Trans Circ Syst Video Technol 20(4):610–615
Lee W, Jung Y, Lee S, Kim J (2007) High speed intra prediction scheme for H.264/AVC. IEEE Trans Consum Electron 53(4):1577–1582
Sahin E, Hamzaoglu I (2007) An efficient hardware architecture for H. 264 intra prediction algorithm. In: Design, automation & test in Europe conference & exhibition, 2007. DATE’07. IEEE, pp 1–6
Huang H, Cao T-Y, Zhang X-W (2008) The enhanced intra prediction algorithm for H.264. In: IEEE conference on image and signal processing, vol 2, pp 161–165
Shah J, Raghunandan KS, Varghese K (2012) HD resolution intra prediction architecture for H.264 decoder. In: IEEE international conference on VLSI design, pp 107–112
Hamdy S, Ibrahim MEA, Abdelhalim Z (2013) VHDL realization of efficient H.264 intra prediction scheme based on best prediction matrix mode. Int J Comput Appl (IJCA) 77:1–7
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2021 The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Pathak, K.C., Darji, A.D., Sarvaiya, J.N. (2021). Novel Low-Complex 4 × 4 and 16 × 16 Intra-prediction Architecture for Error Concealment for H.264. In: Nath, V., Mandal, J.K. (eds) Proceedings of the Fourth International Conference on Microelectronics, Computing and Communication Systems. Lecture Notes in Electrical Engineering, vol 673. Springer, Singapore. https://doi.org/10.1007/978-981-15-5546-6_51
Download citation
DOI: https://doi.org/10.1007/978-981-15-5546-6_51
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-15-5545-9
Online ISBN: 978-981-15-5546-6
eBook Packages: EngineeringEngineering (R0)