FPGA-Based Reconfigurable Architectures for DSP Computations

Abstract

With extensive usage of Field Programmable Gate Arrays (FPGAs), a reconfigurable computing platform enhances the wide variety of Digital Signal Processing (DSP) applications using Lookup Table (LUT), Flip-Flop, and multiplexers. Reconfigurable computation using memory becomes a subject of current research. FPGAs can be reprogrammed an unlimited number of times in which various DSP algorithms can be executed on a single hardware device, just as many different software algorithms can run on a conventional processor. The general architectures for DSP consist of a reconfigurable interconnection, Computational Elements (CEs), and memory. This article discusses on the CE architectures based on Memory (CEMs) and Serial arithmetic (CESs). Reconfigurable computing based on memory is much faster, reliable, and, hence the computation using memory requires less delay and power. The CEMs perform multiplication and addition using LUT and the CESs perform computation using serial arithmetic’s. The results of the CESs, CEMs, and the computational reuse processing elements are compared. The architectures design based on CEMs significantly improves the performance of the previously reported results in terms of speed, area, and power using **linx Virtex-II FPGA, and **linx Vivado software.