Abstract
As the critical dimension (CD) is scaled into nanometer dimensions, operating frequencies exceed a gigahertz, and more functional blocks are added into systems on chip (SoC), interconnect has become a bottleneck in achieving the system performance [1]. In addition, scaling increases the impact of systematic intra-die CD variation (gate and metal linewidth variations) and this variation interacts with the circuit design by degrading circuit speed [2]. One major source of CD variation is the optical lithography process [3]. To determine how the lithography variation impacts circuit performance, this paper introduces a method to incorporate the lithographycaused interconnect linewidth variation in timing simulation. ISCAS benchmark circuits are used to evaluate the circuit performance impact of each optical effect.
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References
N. D. Arora, “Modeling and Characterization of Copper Interconnects for SoC Design,” Proc. SISPAD, 2003, pp. 1–6.
S. R. Nassif, “Modeling and Forecasting of Manufacturing Variations,” Int. Workshop on Statistical Metrology, 2000, pp. 2–10.
M. Choi et al., “Simulation of the Circuit Performance Impact of Lithography in Nanoscale Semiconductor Manufacturing,” Proc. SISPAD, 2003, pp. 219–222.
M. Orshansky et al., “Impact of Spatial Intra-Chip Gate Length Variability on the Performance of High Speed Digital Circuits,” IEEE Trans. CAD, pp. 544–553, May 2002.
V. Mehrotra et al., “A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance,” Proc. DAC, 2000, pp. 172–175.
J. Cong et al., “Analysis and Justification of a Simple, Practical 2 V2-D Capacitance Extraction Methodology,” Proc. DAC, pp. 627–632, 1997.
S-C. Wong et al., “An Empirical Three-Dimensional Crossover Capacitance Model for Multilevel Interconnect VLSI Circuits,” IEEE Trans, on Semiconductor Manufacturing, pp. 219–227, May 2000.
F. Brglez et al., “A neutral netlist of 10 combinatorial benchmark circuits,” Proc. IEEE ISCAS, pp. 695–698, 1985.
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© 2004 Springer-Verlag Wien
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Choi, M., Jia, C., Milor, L. (2004). Simulation of Lithography-caused Gate Length and Interconnect Linewidth Variational Impact on Circuit Performance in Nanoscale Semiconductor Manufacturing. In: Wachutka, G., Schrag, G. (eds) Simulation of Semiconductor Processes and Devices 2004. Springer, Vienna. https://doi.org/10.1007/978-3-7091-0624-2_56
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DOI: https://doi.org/10.1007/978-3-7091-0624-2_56
Publisher Name: Springer, Vienna
Print ISBN: 978-3-7091-7212-4
Online ISBN: 978-3-7091-0624-2
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