Abstract
Power gating has become a popular technique to reduce the ever-increasing leakage power for commercial microprocessors or SoCs. The reactivation energy and delay cost weaken its performance. This paper firstly proposes a novel charge recycling scheme to reduce the transition energy and delay, and then gives its equivalent model. The experiment results show that, comparing to the traditional power gating implementation, it can achieve 19.66% reactivation energy reduction, 9.28% peak leakage reduction, and 23.36% wakeup delay reduction, at 25°C, at the cost of 2.75% area increasing. At the same time, the circuit reliability is improved since the ground bounce reduced.
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© 2012 Springer-Verlag GmbH Berlin Heidelberg
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**, H., Zuocheng, X., **anju, Y., Peixiang, Y., **aomin, J. (2012). A Novel Charge Recycling Scheme in Power Gating Design. In: Lee, G. (eds) Advances in Intelligent Systems. Advances in Intelligent and Soft Computing, vol 138. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-27869-3_19
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DOI: https://doi.org/10.1007/978-3-642-27869-3_19
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-27868-6
Online ISBN: 978-3-642-27869-3
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