Abstract
The multi-layer AHB busmatrix (ML-AHB busmatrix) proposed by ARM is a highly efficient on chip bus that allows parallel access paths between multiple masters and slaves in a system. In this paper, we present one way to improve the arbiter implementation of the ML-AHB busmatrix. We employ the masking mechanism which does not impose any restrictions on arbitration scheme. Therefore, the proposed scheme is applied to the implementation of busmatrixes to support the transaction based arbitrations as well as the transfer based arbitrations. In addition, we could not only enhance the throughput of bus system but also reduce the total area, clock period and power consumption. Experimental results show that the throughput of our busmatrix based on the transfer based fixed priority (round robin) arbitration scheme is increased by 41% (18%) compared with that of the equivalent busmatrix of ARM. Moreover, we could reduce the total area, clock period and power consumption by 22%, 28% and 19% (12%, 15% and 13%) respectively, compared with the busmatrix employing the transfer based fixed priority (round robin) arbitration scheme of ARM.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Jhang, K.-S., Yi, K., Hwang, S.Y.: A two-level on-chip bus system based on multiplexers. In: Yew, P.-C., Xue, J. (eds.) ACSAC 2004. LNCS, vol. 3189, pp. 363–372. Springer, Heidelberg (2004)
Liang, J., Swaminathan, S., Tessier, R.: ASOC: a scalable, single chip communications architecture. In: Parallel Architectures and Compilation Techniques, 15-19 Oct. 2000, pp. 37–46 (2000)
Langen, D., Brinkmann, A., Ruckert, U.: High Level Estimation of the Area and Power Consumption of On-Chip Interconnects. In: Proc. of the 13th Annual IEEE International ASIC/SOC Conference, Sep. 2000, pp. 297–301 (2000)
Sylvester, D., Keutzer, K.: Impact of small process geometries on microarchitectures in systems on a chip. Proceedings of the IEEE 89(4), 467–489 (2001)
Wielage, P., Goossens, K.: Networks on silicon: blessing or nightmare? In: Symp. Digital system design, Dortmund, Germany, 4-6 Sep. 2002, pp. 196–200 (2002)
ARM, AMBA Specification Rev. 2.0. ARM Limited (1999)
AMBA AHB BusMatrix Specification. Document Number ARM DUI 0092C
IBM, 32-bit Processor local bus architecture specification, Version 2.9. IBM Corporation (2001)
Silicore, Wishbone system-on-chip (SoC) interconnection architecture for portable IP cores, Revision: B.1. Silicore corporation (2001)
Sonics, Sonics uNetworks technical overview. Sonics inc. (June 2000)
Flynn, D.: AMBA: Enabling Reusable On-chip Designs. IEEE Micro 17(4), 20–27 (1997)
Kim, N.-J., Lee, H.-J.: Design of AMBATM Wrappers for Multiple-Clock Operations. In: ICCCAS 2004, International Conference on Communications, Circuits and Systems, June 2004, vol. 2, pp. 1438–1442 (2004)
Hwang, S.Y., et al.: An Ameliorated Design Method of ML-AHB BusMatrix. ETRI Journal 28(3), 397–400 (2006)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer Berlin Heidelberg
About this paper
Cite this paper
Hwang, S.Y., Park, H.J., Jhang, K.S. (2007). An Efficient Implementation Method of Arbiter for the ML-AHB Busmatrix. In: Lee, YH., Kim, HN., Kim, J., Park, Y., Yang, L.T., Kim, S.W. (eds) Embedded Software and Systems. ICESS 2007. Lecture Notes in Computer Science, vol 4523. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72685-2_22
Download citation
DOI: https://doi.org/10.1007/978-3-540-72685-2_22
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-72684-5
Online ISBN: 978-3-540-72685-2
eBook Packages: Computer ScienceComputer Science (R0)