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Implementation of Low-Power Full Adder Using GNRFET Technology

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Communication, Networks and Computing (CNC 2022)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1893))

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Abstract

Adders are fundamental components of more complex arithmetic operations, including addition, multiplication, and division, as well as mathematical procedures. The vast majority of these types of systems, adder components is the most critical path that influences the speed of the system. To satisfy these requirements, the adder cell, which is the fundamental structural component, should have its power consumption and propagation delay reduced. Researchers have tried, and continue to try, to create adders that deliver either rapid speed, low power consumption, decreased space, or a combination of these properties. These technical breakthroughs have allowed them to design adders that give one of these benefits. During this research, a variety of digital adders that are functionally identical to Full Adders and GNRFETs manufactured using 32 nm technology were used to construct this area unit. The adder’s equivalent to average power performance parameters and delay is established after being simulated using HSPICE.

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Authors and Affiliations

  1. ITM University, Gwalior, India

    Jay Sutradhar, Shyam Akashe & Sadhana Mishra

Authors
  1. Jay Sutradhar
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  2. Shyam Akashe
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  3. Sadhana Mishra
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Corresponding author

Correspondence to Jay Sutradhar .

Editor information

Editors and Affiliations

  1. ITM University, Gwalior, India

    Ranjeet Singh Tomar

  2. IIIT-Allahabad, Allahabad, Uttar Pradesh, India

    Shekhar Verma

  3. IIIT Lucknow, Lucknow, India

    Brijesh Kumar Chaurasia

  4. IIIT-Allahabad, Allahabad, India

    Vrijendra Singh

  5. Deakin University, Burwood, VIC, Australia

    Jemal H. Abawajy

  6. ITM University, Gwalior, Madhya Pradesh, India

    Shyam Akashe

  7. National Chung Cheng University, Chiayi, Taiwan

    Pao-Ann Hsiung

  8. Aarhus University, Herning, Denmark

    Ramjee Prasad

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Sutradhar, J., Akashe, S., Mishra, S. (2023). Implementation of Low-Power Full Adder Using GNRFET Technology. In: Tomar, R.S., et al. Communication, Networks and Computing. CNC 2022. Communications in Computer and Information Science, vol 1893. Springer, Cham. https://doi.org/10.1007/978-3-031-43140-1_23

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  • DOI: https://doi.org/10.1007/978-3-031-43140-1_23

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-43139-5

  • Online ISBN: 978-3-031-43140-1

  • eBook Packages: Computer ScienceComputer Science (R0)

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