Abstract
The functional verification of VHDL designs is accomplished through simulation using a test bench. A test bench is a VHDL system that instantiates the system to be tested as a component and then generates the input patterns and observes the outputs. VHDL provides a variety of capability to design test benches that can automate stimulus generation and provide automated output checking. These capabilities can be expanded by including packages that take advantage of reading/writing to external I/O. This chapter provides the details of VHDL’s built-in capabilities that allow test benches to be created and some examples of automated stimulus generation and using external files.
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© 2024 The Author(s), under exclusive license to Springer Nature Switzerland AG
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LaMeres, B.J. (2024). Test Benches. In: Quick Start Guide to VHDL. Springer, Cham. https://doi.org/10.1007/978-3-031-42543-1_7
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DOI: https://doi.org/10.1007/978-3-031-42543-1_7
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Publisher Name: Springer, Cham
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Online ISBN: 978-3-031-42543-1
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