Abstract
Dynamic random access memory (DRAM) is one type of semiconductor memory technology that has been used in electronic systems for decades and will survive into the future for its outstanding specifications, including simplicity, low cost, and high-density architecture. However, the access time of DRAM degrades the performance of the utilized system. In- and near-memory computing resolves the memory wall problem, where off-the-shelf, unmodified, and commercial DRAM with minimal modifications are used.
Bitwise operations like logic-AND, bulk initialization, computation acceleration, true random number extraction, and secure key generation are different approaches for DRAM computing. The implementation of DRAM computing paradigms involves programming the memory controller, updating the peripheral circuits, integrating low-overhead blocks near the memory, or a combination of these.
The data is growing faster compared to the computing performance. There is a need for some middle layers to solve the problem
—The Head of DRAM device at SK Hynix
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References
W.A. Wulf, S.A. McKee, Hitting the memory wall: implications of the obvious. ACM SIGARCH Comput. Architect. News 23(1), 20–24 (1995)
K.S. Mohamed, Near-Memory/In-Memory Computing: Pillars and Ladders (Springer, Cham, 2020), pp. 167–186. https://doi.org/10.1007/978-3-030-37224-8_6
V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P.B. Gibbons, M.A. Kozuch, T.C. Mowry, Rowclone: fast and energy-efficient in-dram bulk data copy and initialization, in Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, ser. MICRO-46 (Association for Computing Machinery, New York, 2013), pp. 185–197. https://doi.org/10.1145/2540708.2540725
S. Angizi, D. Fan, Redram: a reconfigurable processing-in-dram platform for accelerating bulk bit-wise operations, in 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (2019), pp. 1–8
J.S. Kim, M. Patel, H. Hassan, O. Mutlu, The dram latency puf: Quickly evaluating physical unclonable functions by exploiting the latency-reliability tradeoff in modern commodity dram devices, in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA) (2018), pp. 194–207.
A. Schaller, W. **ong, N.A. Anagnostopoulos, M.U. Saleem, S. Gabmeyer, B. Škorić, S. Katzenbeisser, J. Szefer, Decay-based dram pufs in commodity devices. IEEE Trans. Depend. Secure Comput. 16(3), 462–475 (2019)
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Abulibdeh, E.E., Mohammad, B., Saleh, H. (2024). In and Near-Memory Computing Using DRAM. In: Mohammad, B., Halawani, Y. (eds) In-Memory Computing Hardware Accelerators for Data-Intensive Applications . Springer, Cham. https://doi.org/10.1007/978-3-031-34233-2_3
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DOI: https://doi.org/10.1007/978-3-031-34233-2_3
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