Abstract
Modern microcontrollers for safety-critical applications with a hard real-time requirement use scratchpad memories assigned directly to the respective processor core to increase the performance. The advantage of scratchpad memories is their deterministic and high access speed. The disadvantage, on the other hand, is the low memory capacity, which means that efficient use is essential for maximum execution speed. For this reason, this article presents a concept that predictively preloads the program scratchpads at fixed preemption points in order to effectively compensate the low memory capacity.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Bertogna, M., Xhani, O., Marinoni, M., Esposito, F., Buttazzo G.: Optimal selection of preemption points to minimize preemption overhead. In: 2011 23rd Euromicro Conference on Real-Time Systems, pp. 217–227 (2011)
Chen, Z.-H., Su, A.: A hardware/software framework for instruction and data scratchpad memory allocation. ACM Trans. Archit. Code Optim. 7, 04 (2010)
Dietrich C., Wägemann P., Ulbrich P., Lohmann, D.: Syswcet: whole-system response-time analysis for fixed-priority real-time systems (outstanding paper). In: 2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 37–48, April 2017
Edwards, S.A., Lee, E.A.: The case for the precision timed (pret) machine. In: Proceedings of the 44th Annual Design Automation Conference, DAC 2007, pp. 264-265, New York, NY, USA, Association for Computing Machinery (2007)
Gai, P., Violante, M.: Automotive embedded software architecture in the multi-core age. In: 2016 21th IEEE European Test Symposium (ETS), pp. 1–8 (2016)
Infineon Technologies AG: AURIX TC3xx Target Specification V2.0.1, 07, 81726 Munich, Germany (2016)
Jungklass, P., Berekovic, M.: Effects of concurrent access to embedded multicore microcontrollers with hard real-time demands. In: 2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES), pp. 1–9 (2018)
Jungklass, P., Berekovic, M.: Memopt: automated memory distribution for multicore microcontrollers with hard real-time requirements. In: 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), pp. 1–7, October 2019
Kim, Y., Broman, D., Cai, J., Shrivastava, A.: Wcet-aware dynamic code management on scratchpads for software-managed multicores. Real-Time Technol. Appl. Proc. 179–188(10), 2014 (2014)
Mancuso, R., Dudko, R., Betti, E., Cesati, M., Caccamo, M., Pellizzoni, R.: Real-time cache management framework for multi-core architectures. In: Proceedings of the 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), RTAS 2013, pp. 45–54, Washington, DC, USA, IEEE Computer Society (2013)
Metzlaff, S., Guliashvili, I., Uhrig, S., Ungerer, T.: A dynamic instruction scratchpad memory for embedded processors managed by hardware. In: Berekovic, M., Fornaciari, W., Brinkschulte, U., Silvano, C. (eds.) ARCS 2011. LNCS, vol. 6566, pp. 122–134. Springer, Heidelberg (2011). https://doi.org/10.1007/978-3-642-19137-4_11
Peng, B., Fisher, N., Bertogna, M.: Explicit preemption placement for real-time conditional code. In: 2014 26th Euromicro Conference on Real-Time Systems, pp. 177–188 (2014)
Puaut, I., Pais, C.: Scratchpad memories vs locked caches in hard real-time systems: a qualitative and quantitative comparison. Institut de Recherche en Informatique et Systèmes Aléatoires - Publication Interne No 1818, 01 (2006)
Rouxel, B., Skalistis, S., Derrien, S., Puaut, I.: Hiding communication delays in contention-free execution for spm-based multi-core architectures. In: Quinton, S. (ed) 31st Euromicro Conference on Real-Time Systems (ECRTS 2019), vol. 133 of Leibniz International Proceedings in Informatics (LIPIcs), pp. 25:1–25:24, Dagstuhl, Germany, Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik (2019)
Saidi, S., Ernst, R., Uhrig, S., Theiling, H., de Dinechin, B.D.: The shift to multicores in real-time and safety-critical systems. In: Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, pp. 220–229. IEEE Press (2015)
Suhendra, V., Mitra, T., Roychoudhury A., Chen, T.: Wcet centric data allocation to scratchpad memory. In: 26th IEEE International Real-Time Systems Symposium, p. 10 p.–232, December 2005
Tabish, R., et al.: A real-time scratchpad-centric OS for multi-core embedded systems. In: 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–11 (2016)
Wehmeyer, L., Marwedel, P.: Influence of memory hierarchies on predictability for time constrained embedded software. In: Design, Automation and Test in Europe, vol. 1, pp. 600–605 (2005)
Yao, G., Pellizzoni, R., Bak, S., Yun, H., Caccamo, M.: Global real-time memory-centric scheduling for multicore systems. IEEE Trans. Comput. 65(9), 2739–2751 (2016)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG
About this paper
Cite this paper
Jungklass, P., Grieger, F., Berekovic, M. (2023). Predictive Preload at Fixed Preemption Points for Microcontrollers with Hard Real-Time Requirements. In: Unger, H., Schaible, M. (eds) Real-time and Autonomous Systems 2022. Real-Time 2022. Lecture Notes in Networks and Systems, vol 674. Springer, Cham. https://doi.org/10.1007/978-3-031-32700-1_5
Download citation
DOI: https://doi.org/10.1007/978-3-031-32700-1_5
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-031-32699-8
Online ISBN: 978-3-031-32700-1
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)