Abstract
This chapter deals with the physical design verification and design signoff procedures of a SOC design. The topics covered in detail are all steps relevant to verification of SOC designs and signoff before ta** out the designs for fabrication. It also deals with the design for manufacturability (DFM), DRC, LEC, and timing checks carried out during design signoff.
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Chakravarthi, V.S. (2022). SoC Physical Design Verification. In: A Practical Approach to VLSI System on Chip (SoC) Design. Springer, Cham. https://doi.org/10.1007/978-3-031-18363-8_9
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DOI: https://doi.org/10.1007/978-3-031-18363-8_9
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Publisher Name: Springer, Cham
Print ISBN: 978-3-031-18362-1
Online ISBN: 978-3-031-18363-8
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