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Machine Learning for Analog Layout

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Machine Learning Applications in Electronic Design Automation

Abstract

The performance of analog circuits is critically dependent on layout parasitics, but layout has traditionally been a manual and time-consuming task. Recent advances in ML have enabled new capabilities to facilitate fast automated placement and routing. This chapter presents an overview of these techniques, including geometric constraint generation and constrained placement and routing. A variety of ML techniques are used in various steps of analog placement and routing, including graph neural networks, random forest methods, support vector machines, graph attention networks, generative adversarial networks, reinforcement learning, and variational autoencoders. This chapter shows how these general ML algorithms are specifically customized to the requirements of optimized analog layout.

This work was supported in part by the DARPA IDEA program (SPAWAR contracts N660011824048 and N669911824049) and NSF CCF-1704758.

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  1. Intel Labs, Hillsboro, OR, USA

    Steven M. Burns, Parijat Mukherjee & Soner Yaldiz

  2. The University of Texas at Austin, Austin, TX, USA

    Tonmoy Dhar, Ramesh Harjani, Nibedita Karmokar, Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Sachin S. Sapatnekar & Arvind K. Sharma

  3. University of Minnesota, Minneapolis, MN, USA

    Jiang Hu, Yaguang Li, Yishuang Lin & Wenbin Xu

  4. Texas A&M University, College Station, TX, USA

    Hao Chen, Mingjie Liu, David Z. Pan & Keren Zhu

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    Haoxing Ren

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    Jiang Hu

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Burns, S.M. et al. (2022). Machine Learning for Analog Layout. In: Ren, H., Hu, J. (eds) Machine Learning Applications in Electronic Design Automation. Springer, Cham. https://doi.org/10.1007/978-3-031-13074-8_17

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