Abstract
In this work we present two case studies of FPGAs in database applications that did not yield the expected results. First, we analyze the issues when synthesizing algorithms that perform small calculations on lots of randomly accessed data, specifically exact lookups in a radix tree. We find that even with manual guidance, the results from high-level synthesis are much slower than the corresponding realization of the algorithm on x86 CPUs. In the second case study, we present a lightweight overlay architecture for streaming query processing which turned out to be too fine-grained to be efficiently placed because the used partitions are quite small. Here, a prototypic implementation revealed resource efficiency limitations related to the interface design of particularly small dynamic reconfiguration partitions. We present approaches to overcome limitations for both case studies.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Awad, M.A., Saman, A., Johnson, R., Farach-Colton, M., Owens, J.D.: Engineering a high-performance GPU B-Tree (2019). https://doi.org/10.1145/3293883.3295706
Leis, V., Kemper, A., Neumann, T.: The adaptive radix tree: ARTful indexing for main-memory databases. In: 2013 IEEE 29th International Conference on Data Engineering (ICDE) (2013). https://doi.org/10.1109/ICDE.2013.6544812
Alam, M., Yoginath, S.B., Perumalla, K.S.: Performance of point and range queries for in-memory databases using radix trees on GPUs. In: 2016 IEEE 18th International Conference on High Performance Computing and Communications (2016). https://doi.org/10.1109/HPCC-SmartCity-DSS.2016.0212
Kaczmarski, K.: B\(^{+}\)-Tree optimized for GPGPU. In: On the Move to Meaningful Internet Systems: OTM 2012 (2012). https://doi.org/10.1007/978-3-642-33615-7_27
Fix, J., Wilkes, A., Skadron, K.: Accelerating braided b+ Tree Searches on a GPU with CUDA (2012)
Farrell, D.: A simple GPU hash table (2020). https://nosferalatu.com/SimpleGPUHashTable.html
Ren, Y., Liao, Z., et al.: A low-latency multi-version key-value store using b-tree on an FPGA-CPU platform (2019). https://doi.org/10.1109/FPL.2019.00058
**ao, X., Shi, T., Vaidya, P., Lee, J.,: R-tree: a hardware implementation. In: Proceedings of the 2008 International Conference on Computer Design, CDES 2008 (2008)
Casper, J., Olukotun, K.: Hardware acceleration of database operations. In: Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2014 (2014)
Sukhwani, B., et al.: Large payload streaming database sort and projection on FPGAs. In: Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing (2013)
R. J. Halstead et al.: Accelerating Join Operation for Relational Databases with FPGAs. In: Proceedings of the IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2013 (2013)
István, Z., Sidler, D., Alonso, G.: Runtime parameterizable regular expression operators for databases. In: Proceedings of the IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016 (2016)
Muhsen Owaida et al.: Centaur: a framework for hybrid CPU-FPGA databases. In: Proceedings of the 2017 International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017 (2017)
Sidler, D., et al.: doppioDB, a hardware accelerated database. In: Proceedings of the 2017 ACM International Conference on Management of Data, SIGMOD 2017 (2017)
Sukhwani, B., et al.: Database analytics acceleration using FPGAs. In: Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques, PACT 2012 (2012)
Salami, B., et al.: AxleDB: a novel programmable query processing engine on FPGA. In: Microprocessors and Microsystems (MICPRO), vol. 51, pp. 142–164 (2017)
Capalija, D., Abdelrahman, T.S.: A high-performance overlay architecture for pipelined execution of data flow graphs. In: Proceedings of the 23rd International Conference on Field programmable Logic and Applications, FPL 2013 (2013)
Becher, A., Herrmann, A., Wildermann, S., Teich, J.: ReProVide: towards utilizing heterogeneous partially reconfigurable architectures or near-memory data processing. In: Proceedings of the 1st Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors, NoDMC 2019 (2019)
Ziener, D., et al.: FPGA-based dynamically reconfigurable SQL query processing. ACM Trans. Reconfigurable Technol. Syst. (TRETS) 9(4), 1–24 (2016)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2022 Springer Nature Switzerland AG
About this paper
Cite this paper
Drewes, A., Koppehel, M., Pionteck, T. (2022). Dead-Ends in FPGAs for Database Acceleration. In: Orailoglu, A., Jung, M., Reichenbach, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science, vol 13227. Springer, Cham. https://doi.org/10.1007/978-3-031-04580-6_33
Download citation
DOI: https://doi.org/10.1007/978-3-031-04580-6_33
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-031-04579-0
Online ISBN: 978-3-031-04580-6
eBook Packages: Computer ScienceComputer Science (R0)