Emerging Memory Devices for Neuromorphic Systems

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Neuromorphic Computing Principles and Organization

Abstract

To design a neuromorphic system in hardware, it is imperative to develop artificial neurons that mimic biological neurons and artificial synapses that emulate biological synapses. Recently, numerous efforts have been made to realize artificial synapses using post-CMOS devices, including resistive random access memory (ReRAM), ferroelectric field-effect transistor (FeFET), phase change memory devices, magnetoresistive random access memory (MRAM), etc. A non-CMOS neuron based on emerging devices has also been investigated. This chapter discusses the major emerging memory technologies that promise neuromorphic computing and highlight some recent significant progress on device studies. The advantages and challenges for each device technology are also discussed.

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References

  1. Akopyan F, Sawada J, Cassidy A, Alvarez-Icaza R, Arthur J, Merolla P, Imam N, Nakamura Y, Datta P, Nam G, Taba B, Beakes M, Brezzo B, Kuang JB, Manohar R, Risk WP, Jackson B, Modha DS (2015) Truenorth: design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip. IEEE Trans Comput-Aid Des Integr Circuits Syst 34(10):1537–1557

    Article  Google Scholar 

  2. Ben Abdallah A, Dang KN (2021) Toward robust cognitive 3d brain-inspired cross-paradigm system. Front Neurosci 15:795

    Article  Google Scholar 

  3. Bichler O, Suri M, Querlioz D, Vuillaume D, DeSalvo B, Gamrat C (2012) Visual pattern extraction using energy-efficient “2-PCM synapse” neuromorphic architecture. IEEE Trans Electron Dev 59(8):2206–2214

    Article  Google Scholar 

  4. Chang M, Rosenfeld P, Lu S, Jacob B (2013) Technology comparison for large last-level caches (L3CS): low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. In: 2013 IEEE 19th international symposium on high performance computer architecture (HPCA), pp 143–154

    Google Scholar 

  5. Close G, Frey U, Breitwisch M, Lung H, Lam C, Hagleitner C, Eleftheriou E (2010) Device, circuit and system-level analysis of noise in multi-bit phase-change memory. In: 2010 international electron devices meeting. IEEE, Piscataway, pp 29–5

    Google Scholar 

  6. Dang KN, Abdallah AB (2019) An efficient software-hardware design framework for spiking neural network systems. In: The international conference on internet of things, embedded systems and communications (IINTEC 2019)

    Google Scholar 

  7. Davies M, Srinivasa N, Lin T, Chinya G, Cao Y, Choday SH, Dimou G, Joshi P, Imam N, Jain S, Liao Y, Lin C, Lines A, Liu R, Mathaikutty D, McCoy S, Paul A, Tse J, Venkataramanan G, Weng Y, Wild A, Yang Y, Wang H (2018) Loihi: a neuromorphic manycore processor with on-chip learning. IEEE Micro 38(1):82–99

    Article  Google Scholar 

  8. Frenkel C, Lefebvre M, Legat JD, Bol D (2018) A 0.086-mm2 12.7-pj/sop 64k-synapse 256-neuron online-learning digital spiking neuromorphic processor in 28-nm CMOS. IEEE Trans Biomed Circuits Syst 13(1):145–158

    Google Scholar 

  9. Frenkel C, Legat J, Bol D (2019) Morphic: a 65-nm 738k-synapse/mm2 quad-core binary-weight digital neuromorphic processor with stochastic spike-driven online learning. IEEE Trans Biomed Circuits Syst 13:999–1010

    Article  Google Scholar 

  10. Furber SB, Lester DR, Plana LA, Garside JD, Painkras E, Temple S, Brown AD (2013) Overview of the spinnaker system architecture. IEEE Trans Comput 62(12):2454–2467

    Article  MathSciNet  Google Scholar 

  11. Grollier J, Querlioz D, Camsari K, Everschor-Sitte K, Fukami S, Stiles MD (2020) Neuromorphic spintronics. Nat Electron 3(7):360–370

    Article  Google Scholar 

  12. Ikechukwu OM, Dang KN, Abdallah AB (2021) On the design of a fault-tolerant scalable three dimensional NoC-based digital neuromorphic system with on-chip learning. IEEE Access 9:64331–64345

    Article  Google Scholar 

  13. Joshi V, Le Gallo M, Haefeli S, Boybat I, Nandakumar SR, Piveteau C, Dazzi M, Rajendran B, Sebastian A, Eleftheriou E (2020) Accurate deep neural network inference using computational phase-change memory. Nat Commun 11(1):1–13

    Article  Google Scholar 

  14. Nandakumar S, Le Gallo M, Boybat I, Rajendran B, Sebastian A, Eleftheriou E (2018) A phase-change memory model for neuromorphic computing. J Appl Phys 124(15):152135

    Article  Google Scholar 

  15. Pérez E, Cristian Zambelli MKM, Olivo P, Wenger C (2019) Toward reliable multi-level operation in rram arrays: improving post-algorithm stability and assessing endurance/data retention. IEEE J Electron Dev Soc 7:740–747

    Article  Google Scholar 

  16. Seo J, Brezzo B, Liu Y, Parker BD, Esser SK, Montoye RK, Rajendran B, Tierno JA, Chang L, Modha DS, Friedman DJ (2011) A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. In: 2011 IEEE custom integrated circuits conference (CICC), pp. 1–4

    Google Scholar 

  17. Tosson AMS, Yu S, Anis MH, Wei L (2018) Proposing a solution for single-event upset in 1T1R RRAM memory arrays. IEEE Trans Nucl Sci 65(6), 1239–1247

    Article  Google Scholar 

  18. Yang JJ, Strukov DB, Stewart DR (2013) Memristive devices for computing. Nat Nanotechnol 8(1):13

    Article  Google Scholar 

  19. Zhang Q, Wu H, Yao P, Zhang W, Gao B, Deng N, Qian H (2018) Sign backpropagation: an on-chip learning algorithm for analog RRAM neuromorphic computing systems. Neural Netw 108:217–223

    Article  Google Scholar 

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Correspondence to Abderazek Ben Abdallah or Khanh N. Dang .

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Ben Abdallah, A., N. Dang, K. (2022). Emerging Memory Devices for Neuromorphic Systems. In: Neuromorphic Computing Principles and Organization. Springer, Cham. https://doi.org/10.1007/978-3-030-92525-3_4

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  • DOI: https://doi.org/10.1007/978-3-030-92525-3_4

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-92524-6

  • Online ISBN: 978-3-030-92525-3

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