Neuromorphic System Design Fundamentals

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Neuromorphic Computing Principles and Organization

Abstract

The neuromorphic computing paradigm has the potential to improve the efficiency of computational tasks. Unlike the typical artificial neural networks (ANNs), where neurons fire at each propagation cycle, the neurons in a neuromorphic neural networks model, named spiking neural networks (SNNs), fire only when their membrane potential reaches a certain threshold. Spiking neurons are only activated when sufficient signals are integrated from other neurons, which leads to sparse neural activities at the network level. Furthermore, their asynchronous event-driven operations, distributed memory, and massive parallelism significantly accelerate information processing and reduce energy consumption in many applications (i.e., pattern recognition, object detection, navigation, motor control, and so on). The key design challenges of neuromorphic systems include: how the organization of individual neurons, circuits, applications, and overall architectures enable energy-efficient computations, how information is represented, and how adaptation to local and evolutionary changes are facilitated. Moreover, a massively parallel neuromorphic architecture will require building small-sized neuro processing cores with low-power consumption, efficient neuron coding schemes, and a lightweight on-chip learning algorithm, which is also a challenges. This chapter covers fundamental design principles to build an efficient neuromorphic system in hardware.

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References

  1. Bai K, Yi Y (2019) Opening the “black box” of silicon chip design in neuromorphic computing. In: Bio-inspired technology. IntechOpen

    Google Scholar 

  2. Balaji A, Adiraju P, Kashyap HJ, Das A, Krichmar JL, Dutt ND, Catthoor F (2020) PyCARL: a PyNN interface for hardware-software co-simulation of spiking neural network. Preprint, ar**v:2003.09696

    Google Scholar 

  3. Başar E (2013) Brain oscillations in neuropsychiatric disease. Dialogues Clin Neurosci 15(3):291

    Article  Google Scholar 

  4. Ben Abdallah A, Dang KN (2021) Toward robust cognitive 3d brain-inspired cross-paradigm system. Front Neurosci 15:795

    Article  Google Scholar 

  5. Bhaskar A (2017) Design and analysis of low power SRAM cells. In: 2017 Innovations in power and advanced computing technologies (i-PACT). IEEE, Piscataway, pp 1–5

    Google Scholar 

  6. Boahen KA (1998) Communicating neuronal ensembles between neuromorphic chips. In: Neuromorphic systems engineering. Springer, Berlin, pp 229–259

    Chapter  Google Scholar 

  7. Brader JM, Senn W, Fusi S (2007) Learning real-world stimuli in a neural network with spike-driven synaptic dynamics. Neural Comput 19(11):2881–2912

    Article  MathSciNet  MATH  Google Scholar 

  8. Chang M, Rosenfeld P, Lu S, Jacob B (2013) Technology comparison for large last-level caches (L3Cs): low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. In: 2013 IEEE 19th international symposium on high performance computer architecture (HPCA), Feb 2013, pp 143–154

    Google Scholar 

  9. Deiss SR, Douglas RJ, Whatley AM, Maass W (1999) A pulse-coded communications infrastructure for neuromorphic systems. In: Pulsed neural networks, pp 157–178

    Google Scholar 

  10. Diehl PU, Neil D, Binas J, Cook M, Liu S, Pfeiffer M (2015) Fast-classifying, high-accuracy spiking deep networks through weight and threshold balancing. In: 2015 International joint conference on neural networks (IJCNN), July 2015, pp 1–8

    Google Scholar 

  11. Frenkel C, Legat J, Bol D (2019) Morphic: a 65-nm 738k-synapse/mm2 quad-core binary-weight digital neuromorphic processor with stochastic spike-driven online learning. IEEE Trans Biomed Circuits Syst 13(5):999–1010

    Article  Google Scholar 

  12. Gerstner W, Kistler WM, Naud R, Paninski L (2014) Neuronal dynamics: from single neurons to networks and models of cognition. Cambridge University Press, Cambridge

    Book  Google Scholar 

  13. Göltz J, Baumbach A, Billaudelle S, Breitwieser O, Dold D, Kriener L, Kungl AF, Senn W, Schemmel J, Meier K et al (2019) Fast and deep neuromorphic learning with time-to-first-spike coding. Preprint, ar**v:1912.11443

    Google Scholar 

  14. Hakim N, Vogel EK (2018) Phase-coding memories in mind. PLoS Biol 16(8):e3000012

    Article  Google Scholar 

  15. Iannella N, Launey T, Tanaka S (2010) Spike timing-dependent plasticity as the origin of the formation of clustered synaptic efficacy engrams. Front Comput Neuros 4:21

    Google Scholar 

  16. Ikechukwu OM, Dang KN, Abdallah AB (2021) On the design of a fault-tolerant scalable three dimensional NoC-based digital neuromorphic system with on-chip learning. IEEE Access 9:64331–64345

    Article  Google Scholar 

  17. Indiveri G, Chicca E, Douglas R (2006) A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity. IEEE Trans Neural Netw 17(1):211–221

    Article  Google Scholar 

  18. Izhikevich E (2003) Simple model of spiking neurons. IEEE Trans Neural Netw 14(6):1569–1572

    Article  MathSciNet  Google Scholar 

  19. Lazzaro J, Wawrzynek J, Mahowald M, Sivilotti M, Gillespie D (1993) Silicon auditory processors as computer peripherals. IEEE Trans Neural Netw 4(3):523–528

    Article  Google Scholar 

  20. Luo T, Wang X, Qu C, Lee MKF, Tang WT, Wong W-F, Goh RSM (2018) An FPGA-based hardware emulator for neuromorphic chip with RRAM. IEEE Trans Comput Aided Des Integr Circuits Syst 39(2):438–450

    Article  Google Scholar 

  21. Majumder T, Suri M, Shekhar V (2015) NoC router using STT-MRAM based hybrid buffers with error correction and limited flit retransmission. In: 2015 IEEE international symposium on circuits and systems (ISCAS). IEEE, Piscataway, pp 2305–2308

    Chapter  Google Scholar 

  22. Mayr CG, Partzsch J (2010) Rate and pulse based plasticity governed by local synaptic state variables. Front Synaptic Neurosci 2:33

    Article  Google Scholar 

  23. Mead C (1990) Neuromorphic electronic systems. Proc IEEE 78(10):1629–1636

    Article  Google Scholar 

  24. Merolla PA, Arthur JV, Alvarez-Icaza R, Cassidy AS, Sawada J, Akopyan F, Jackson BL, Imam N, Guo C, Nakamura Y et al (2014) A million spiking-neuron integrated circuit with a scalable communication network and interface. Science 345(6197):668–673

    Article  Google Scholar 

  25. Mortara A, Vittoz EA, Venier P (1995) A communication scheme for analog VLSI perceptive systems. IEEE J Solid-State Circuits 30(6):660–669

    Article  Google Scholar 

  26. Pan Z, Wu J, Zhang M, Li H, Chua Y (2019) Neural population coding for effective temporal classification. In: 2019 International joint conference on neural networks (IJCNN). IEEE, Piscataway, pp 1–8

    Google Scholar 

  27. Park J, Yu T, Joshi S, Maier C, Cauwenberghs G (2016) Hierarchical address event routing for reconfigurable large-scale neuromorphic systems. IEEE Trans Neural Netw Learn Syst 28(10):2408–2422

    Article  MathSciNet  Google Scholar 

  28. Park S, Kim S, Na B, Yoon S (2020) T2fsnn: deep spiking neural networks with time-to-first-spike coding. Preprint, ar**v:2003.11741

    Google Scholar 

  29. Ponulak F, Kasiński A (2010) Supervised learning in spiking neural networks with resume: sequence learning, classification, and spike shifting. Neural Comput 22(2):467–510

    Article  MathSciNet  MATH  Google Scholar 

  30. Rahimi Azghadi M, Iannella N, Al-Sarawi SF, Indiveri G, Abbott D (2014) Spike-based synaptic plasticity in silicon: Design, implementation, application, and challenges. Proc IEEE 102(5):717–737

    Article  Google Scholar 

  31. Rueckauer B, Lungu I-A, Hu Y, Pfeiffer M, Liu S-C (2017) Conversion of continuous-valued deep networks to efficient event-driven networks for image classification. Front Neurosci 11:682

    Article  Google Scholar 

  32. Sengupta B, Laughlin SB, Niven JE (2014) Consequences of converting graded to action potentials upon neural information coding and energy efficiency. PLoS Comput Biol 10(1):1–18

    Article  Google Scholar 

  33. Seo J-s, Brezzo B, Liu Y, Parker BD, Esser SK, Montoye RK, Rajendran B, Tierno JA, Chang L, Modha DS et al (2011) A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. In: 2011 IEEE custom integrated circuits conference (CICC). IEEE, Piscataway, pp 1–4

    Google Scholar 

  34. Shoushun C, Bermak A (2005) A low power CMOS imager based on time-to-first-spike encoding and fair AER. In: 2005 IEEE international symposium on circuits and systems. IEEE, Piscataway, pp 5306–5309

    Chapter  Google Scholar 

  35. Sjostrom PJ, Rancz EA, Roth A, Hausser M (2008) Dendritic excitability and synaptic plasticity. Physiol Rev 88(2):769–840

    Article  Google Scholar 

  36. Stein RB, Gossen ER, Jones KE (2005) Neuronal variability: noise or part of the signal? Nat Rev Neurosci 6(5):389–397

    Article  Google Scholar 

  37. Thorpe S, Gautrais J (1998) Rank order coding. In: Computational neuroscience. Springer, Berlin, pp 113–118

    Chapter  Google Scholar 

  38. Thorpe S, Delorme A, Van Rullen R (2001) Spike-based strategies for rapid processing. Neural Netw 14(6–7):715–725

    Article  Google Scholar 

  39. Vainbrand D, Ginosar R (2010) Comparing NoC architectures for neural networks. In: 2010 IEEE 26-th convention of electrical and electronics engineers in Israel. IEEE, Piscataway, pp 000660–000664

    Google Scholar 

  40. Vainbrand D, Ginosar R (2010) Network-on-chip architectures for neural networks. In: 2010 Fourth ACM/IEEE international symposium on networks-on-chip. IEEE, Piscataway, pp 135–144

    Chapter  Google Scholar 

  41. van Schaik A, Liu S-C (2005) AER EAR: a matched silicon cochlea pair with address event representation interface. In: 2005 IEEE international symposium on circuits and systems. IEEE, Piscataway, pp 4213–4216

    Chapter  Google Scholar 

  42. VanRullen R, Guyonneau R, Thorpe SJ (2005) Spike times make sense. Trends Neurosci 28(1):1–4

    Article  Google Scholar 

  43. Vincent AF, Larroque J, Locatelli N, Romdhane NB, Bichler O, Gamrat C, Zhao WS, Klein J-O, Galdin-Retailleau S, Querlioz D (2015) Spin-transfer torque magnetic memory as a stochastic memristive synapse for neuromorphic systems. IEEE Trans Biomed Circuits Syst 9(2):166–174

    Article  Google Scholar 

  44. Vu TH, Ikechukwu OM, Abdallah AB (2019) Fault-tolerant spike routing algorithm and architecture for three dimensional NoC-based neuromorphic systems. IEEE Access 7:90436–90452

    Article  Google Scholar 

  45. Vu TH, Murakami Y, Abdallah AB (2019) Graceful fault-tolerant on-chip spike routing algorithm for mesh-based spiking neural networks. In: 2019 2nd International conference on intelligent autonomous systems (ICoIAS), Singapore, Feb 2019

    Google Scholar 

  46. Vu TH, Murakami Y, Abdallah AB (2019) A low-latency tree-based multicast spike routing for scalable multicore neuromorphic chips. In: ACM 5th international conference of computing for engineering and sciences, Hammamet, Tunisia, July 2019

    Google Scholar 

  47. Vu TH, Okuyama Y, Abdallah AB (2019) Comprehensive analytic performance assessment and k-means based multicast routing algorithm and architecture for 3d-NoC of spiking neurons. ACM J Emerg Technol Comput Syst 15(4):1–28

    Article  Google Scholar 

  48. **a L, Huangfu W, Tang T, Yin X, Chakrabarty K, **e Y, Wang Y, Yang H (2017) Stuck-at fault tolerance in RRAM computing systems. IEEE J Emerg Sel Top Circuits Syst 8(1):102–115

    Article  Google Scholar 

  49. Yin S, Venkataramanaiah S, Chen G, Krishnamurthy R, Cao Y, Chakrabarti C, Sun Seo J (2018) Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. In: 2017 IEEE biomedical circuits and systems conference, BioCAS 2017 - Proceedings, Jan, vol 2018. Institute of Electrical and Electronics Engineers, Piscataway, pp 1–4

    Google Scholar 

  50. Zhao, C, Wysocki BT, Thiem CD, McDonald NR, Li J, Liu L, Yi Y (2016) Energy efficient spiking temporal encoder design for neuromorphic computing systems. IEEE Trans Multi-Scale Comput Syst 2(4):265–276

    Article  Google Scholar 

  51. Zhao C, Yi Y, Li J, Fu X, Liu L (2017) Interspike-interval-based analog spike-time-dependent encoder for neuromorphic processors. IEEE Trans Very Large Scale Integr Syst 25(8):2193–2205

    Article  Google Scholar 

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Correspondence to Abderazek Ben Abdallah or Khanh N. Dang .

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Ben Abdallah, A., N. Dang, K. (2022). Neuromorphic System Design Fundamentals. In: Neuromorphic Computing Principles and Organization. Springer, Cham. https://doi.org/10.1007/978-3-030-92525-3_2

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  • DOI: https://doi.org/10.1007/978-3-030-92525-3_2

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