Abstract
Integer adders are central elements of processor designs, as they are used by a wide variety of floating-point and integer arithmetic instructions as well as memory addressing and program counting. Since it is important that the operation be performed for common bit-widths within a single cycle, the execution speed of an adder is often a dominant factor in determining the processor’s clock speed and is therefore generally a more important consideration than chip area or power consumption. Integer addition is often treated by the RTL designer as a primitive operation to be implemented by a logic synthesis tool (see, for example, the adder of Chap. 17). This amounts to a selection from a library of predefined adder modules, based on width and timing requirements. If other considerations are more important, however, as in the context of a GPU or a small-core CPU, the designer may prefer to exercise more control and hand-code a suitable solution (as in the GPU adder of Chap. 22).
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References
D. R. Lutz. The Power of the Half-Adder Form. PhD thesis, The Ohio State University, 1996.
V. Oklobdzija. An algorithmic and novel design of a leading zero detector circuit: Comparison with logic synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(1):124–128, March 1994.
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Russinoff, D.M. (2022). Addition. In: Formal Verification of Floating-Point Hardware Design. Springer, Cham. https://doi.org/10.1007/978-3-030-87181-9_8
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DOI: https://doi.org/10.1007/978-3-030-87181-9_8
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