Abstract
CGRAs traditionally use a control scheme that is either completely centralized or completely decentralized. Systolic arrays operating in lock-step are an example of centralized control; lightweight processors performing their own instruction decoding and control flow are an example of decentralized control. The Blocks CGRA allows the designer to choose the granularity of the control scheme. In Blocks, instruction decoders can be connected to one or more function units. Furthermore, multiple groups of instruction decoders can be configured to operate in lock-step. This allows construction of vector lanes, multiple function units under the control of a single instruction decoder, as well as issue slots, by using multiple instruction decoders in lock-step, as well as multi-processor systems. In order to implement this Blocks uses two circuit switched reconfigurable networks. This chapter describes the Blocks architecture in depth with respect to the networks, the memory hierarchy, the function units, and the processor structures that can be configured onto Blocks.
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Wijtvliet, M., Corporaal, H., Kumar, A. (2022). Concept of the Blocks Architecture. In: Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures . Springer, Cham. https://doi.org/10.1007/978-3-030-79774-4_3
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DOI: https://doi.org/10.1007/978-3-030-79774-4_3
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