Abstract
In order to improve the performance of arithmetic VLSI system, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode (MVCM) by using dynamic source-coupled logic (SCL). Its key components, the comparator and the output generator, are both based on differential-pair circuit (DPC), and the latter is constructed by using structure of DPC trees. The pre-charge evaluates logic style, makes steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source-coupled logic and differential-pair circuit makes its power lower and its structure more compact. The performance is evaluated by HSPICE simulation with 0.18 μm CMOS technology. The power dissipation, transistor numbers and delay are superior to corresponding binary CMOS implementation. Multiple-valued logic is the potential solution for the high performance arithmetic VLSI system in the future.
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References
Iwai H (1999) CMOS technology-year 2010 and beyond. IEEE Solid-State circuits SC-34, 3, 357/366
Geer D (2005) Chip makers turn to multi-core processors. Computer 38(5):11–13
Zhirnov VV (2005) Emerging research logic devices. IEEE Circuits Devices Mag 37–46
Venkatraman V, Burleson W (2008) An energy-efficient multi-bit quaternary current-mode signaling for on-chip interconnects. In: Proceedings of the custom integrated circuits conference, pp 301–304
Matsuura T, Shirahama H (2009) Timing variation aware multiple-valued current-mode circuit for a low-power pipelined system. In: 39th international symposium on multiple-valued logic. ISMVL 2009, pp 60–65
Natsui M, Arimitsu T, Hanyu (2010) Low-energy pipelined multiple-valued current-mode circuit with 8-level static current-source control. In: Proceedings of the international symposium on multiple-valued logic, ISMVL 2010, pp 235–240
Shirahama H, Mochizuki A, Hanyu T, Nakajima M, Arimoto K (2007) Design of a processing element based on quaternary differential logic for a multi-core simd processor. In: Proceedings of 37th IEEE international symposium on multiple-valued logic, May 2007
Jerraya A et al (2005) Multiprocessor systems-on-chips. Computer 38(7):36–40
Geer D (2005) Chip makers turn to multicore processors. Computer 38(5):11–13
Ike T, Hanyu T, Kameyama M (2002) Fully source-coupled logic based multiple-valued VLSI. In: Proceedings of 32nd IEEE international symposium on multiple-valued logic, 270/275, Boston, Massachusetts, U S A, May 2002
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© 2012 Springer-Verlag London Limited
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Wu, H., Zhong, S., Cai, Q., **a, Q., Chen, Y. (2012). Design of Quaternary Logic Circuits Based on Multiple-Valued Current Mode. In: Wang, X., Wang, F., Zhong, S. (eds) Electrical, Information Engineering and Mechatronics 2011. Lecture Notes in Electrical Engineering, vol 138. Springer, London. https://doi.org/10.1007/978-1-4471-2467-2_56
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DOI: https://doi.org/10.1007/978-1-4471-2467-2_56
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