Abstract
As demands for secure communication bandwidth grow, efficient processing of cryptographic server at the host has become a constraint that prevents the achievement of acceptable secure services at large e-commerce and e-governments. To overcome this limitation, this paper proposes an innovative design in cryptographic server architecture, which based on the hardware of high performance and programmable secure crypto module. The architecture provides a well scalability framework by using a general device API, as well as obtains high performance by carrying cryptography computations in parallel between crypto chips in crypto modules. The system is implemented on an IBM Services345 and hardware of crypto modules. Preliminary measurements are also performed to study the trade-off between numbers of crypto modules parallel computing and performance of generate 1024-bit RSA digital signature. Results indicate that the system implemented by the architecture with high performance and scalability.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Smith, S.W., Weingart, S.H.: Building a High Performance, Programmable Secure Coprocessors. Computer Networks (Special Issue on Computer Network Security) 31, 831–860 (1999)
Amold, T.W., Van Doorn, L.P.: The PCIXCC:A new cryptographic coprocessor for the IBM eServer. IBM Journal of Research and Development 31, 475–487 (2004)
PKCS #11 v2.11. Cryptographic Token Interface Standard. RSA Laboratories (2001)
Peter, G.: The Design of a Cryptographic Security Architecture. In: Proceedings of the 8th Usenix Security Symposium. USENIX, Washington, D.C., pp. 153–169 (1999)
John, L.: Generic Security Service Application Programming Interface. In: RFC 2078 (1997)
Johnson, D.B., Dolan, G.M.: Transaction security system extensions to the common cryptographic architecture. IBM Journal of System 30, 230–243 (1991)
Wu, L., Weaver, T.A.: CryptoManiac:A Fast Flexible Architecture for Secure Communication. In: Proceedings of the 28th International Symposium on Computer Architecture (ISCA 2001), pp. 110–119. IEEE CS Press, Sweden (2001)
Kuo, H., Verbauwhede, I.M.: Architectural Optimization for a 1.82 Gb/s VLSI Implementation of the AES Rijndael Algorithm. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 51–64. Springer, Heidelberg (2001)
Lennon, R.E.: Cryptography architecture for information security. IBM Journal of System 17, 138–150 (1978)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Rong, X., Gao, X., Su, R., Zhou, L. (2005). Design and Implementation of a Parallel Crypto Server. In: Hao, Y., et al. Computational Intelligence and Security. CIS 2005. Lecture Notes in Computer Science(), vol 3802. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11596981_58
Download citation
DOI: https://doi.org/10.1007/11596981_58
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30819-5
Online ISBN: 978-3-540-31598-8
eBook Packages: Computer ScienceComputer Science (R0)