Monolithic CMOS Fractional-N Frequency Synthesizer Design for High Spectral Purity

Abstract

Does fractional-N synthesis offer the way out for monolithic CMOS integration of high-quality transceivers? That is the question raised and answered in this document based on the most critical criteria influenced by extending the integer phase-locked loop (PLL) with fractional capabilities: phase noise and spurious tones, i.e. the spectral purity, integratability and agility. Linear system theory is applied to uncover the fundamental bandwidth limitations imposed by the δσ noise in typical PLLs. Practice however proves the linear approach inaccurate. Therefore, a non-linear analysis method is developed, that swiftly predicts the effects of PLL non-linearities on the spectral purity. Serious in-band noise leakage and re-emerging spurious tones can be observed and are in close correspondence with experimental results. Both methods are applied to compare MASH and single-loop δσ modulators in fractional-N synthesis. Based on the analyses, practical circuit design guidelines are compiled and applied to design a monolithic δσ-controlled fractional-N PLL in 0.25μm CMOS that complies to the stringent DCS-1800 cellular specifications.