Abstract
High-speed serial digital backplane transceivers must equalize broadband channel loss at frequencies up to several GHz. Power dissipation must be minimized to allow for integration of many transceivers on a single IC. This paper will include a system level overview of the electrical backplanes typical in state-of-the-art network equipment. The signal integrity considerations applicable to this channel will be presented. Mixed-signal circuit approaches to implement highly integrated backplane transceivers that are interoperable with conventional binary signaling will be discussed. The tradeoffs of multi-level signaling for future applications will also be covered.
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© 2003 Kluwer Academic Publishers
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Tam, K., Ellersick, W., Soenneker, R. (2003). Backplane Transceivers. In: van Roermund, A., Steyaert, M., Huijsing, J.H. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/0-306-48707-1_18
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DOI: https://doi.org/10.1007/0-306-48707-1_18
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7559-9
Online ISBN: 978-0-306-48707-1
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