Abstract
FinFET do** via implantation at room temperature could result in Fin damage within the Fin body and degrade Fin device performance. Heated implantation techniques are developed on Thermion® VIISta platform implanters to address the detrimental effects on devices caused by the damage, such as LDD formation. For well formation, there are two implant-based approaches: (1) using implant through Fin scheme, the implant damage can result in Fin damage especially for scaled Fin technology with elevated well implant dose required to suppress sub-fin leakage; (2) using the implant/epi scheme, the residual damage before epi process could result in Fin crystal defects and therefore be detrimental to device performance. In this paper, the heated implantation technique was applied to typical well formation conditions. Post heated implant wafers were characterized with TW damage, Rs for activation, and SIMS for profile response at various implant temperatures for boron (B), phosphorus (P), and arsenic (As). TCAD simulations are explored to understand the Fin well requirement to suppress sub-Fin leakage with evolved Fin technologies. For implant/Epi scheme, TCAD simulations predict the damage control required for multiple well/punch-through implants. Experimental studies showed damage-free epi growth with elevated implant temperatures.
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Guo, B.N., Pradhan, N., Zhang, Y. et al. The scaled FinFET well formation using heated implantation. MRS Advances 7, 1468–1471 (2022). https://doi.org/10.1557/s43580-022-00413-0
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DOI: https://doi.org/10.1557/s43580-022-00413-0