Abstract
In this study, we report a new wafer bonding technique for the integration of GaAs- and InP-based optical devices with prefabricated Si electronic devices in hybrid circuit technology. This technique uses a Au-Ge eutectic alloy as the bonding materials between GaAs and Si wafers, and between InP and Si wafers. This process takes advantage of the low temperature solid-state reactions at GaAs/Au-Ge, InP/Au-Ge, and Si/Au-Ge interfaces. The bonding was carried out by annealing the samples at 280-300°C in an alloying furnace. The reliability of the joined wafers was evaluated by both cleavage test and standard thermal cycling test. The joining interfaces were characterized by scanning electron microscopy and transmission electron microscopy. The results reveal that the bonding is achieved by low temperature reactions at the GaAs/Au-Ge and InP/Au-Ge interfaces as well as solid-phase epitaxial regrowth at the Si interfaces. The joined structure has very good integrity.
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Acknowledgments
The authors (Z.Ma and L.H.Allen) would like to acknowledge the funding support from the Joint Services Electronics Programs (JSEP) under contract N00014-90-J-1270 and a grant from the Petroleum Research Fund ACS-PRF#25422-G5. The authors (G.L.Zhou, T.C.Shen, M.E.Lin, and H.Morkoç) would like to thank the funding support from ONR under grant # N0OO14-92-J-1258 and acknowledge Dr.Y.S. Park as the technical monitor. Some of the materials characterization were carried out in the Center for Microanalysis of Materials at University of Illinois, which is supported by the Department of Energy.
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Ma, Z., Zhou, G., Shen, T. et al. Wafer Bonding for Hybrid Circuit Technology Using Solid-State Reactions. MRS Online Proceedings Library 314, 241–245 (1993). https://doi.org/10.1557/PROC-314-241
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DOI: https://doi.org/10.1557/PROC-314-241