Abstract
The results of the concentration method development for the data coming from the detector integrated circuits, intended for the experimental facilities MPD and BM@N, are presented. Charged particle detectors at these installations are characterized by a high granularity and accuracy of the detecting equipment. That results in a large data volume and the need to transfer processed data at a gigabit rate. Therefore, ASIC of the data concentrator requires both a high integration and use of specific structure as well as circuit and layout to provide an increased radiation tolerance. A specific feature of the ASIC is its ability to operate in the actual radiation background of the experiments estimated by up to 100 kRad in terms of immunity to heavy charged particles. In order to approbate the method and solutions on improvement of the radiation tolerance, the design results of a prototype 65 nm CMOS ASIC for read-out the signals from two SAMPA front-end chips cards are described. ASIC is intended for data receipt, concentration and subsequent transmission at a rate of 2.56 Gbit/s over micro-coaxial cables of 1 m length.
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This work was supported by the Russian Foundation for Basic Research (project no. 18-02-40093).
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Atkin, E., Azarov, D., Normanov, D. et al. Development of Data Concentration Method and Its Implementation in a Radiation-Tolerant CMOS Application Specific Integrated Circuit. Phys. Part. Nuclei 52, 752–756 (2021). https://doi.org/10.1134/S1063779621040080
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DOI: https://doi.org/10.1134/S1063779621040080