Introduction

Power devices are essential building blocks for high-efficiency energy conversion in power electronics systems. The market size of power semiconductor devices has reached US$40 billion driven by applications like electric vehicles, data centers, electric grids, and renewable energy processing1. Deployment of new semiconductors is a fundamental driving force to advance power electronics. The last decade witnesses the success of wide bandgap (WBG) semiconductors, e.g., gallium nitride (GaN) and silicon carbide (SiC)2,3,4,5. On the horizon, ultrawide bandgap (UWBG) semiconductors hold tremendous promises for the next-generation power electronics6,7,8,9.

Power devices operate as switches between the high blocking voltage and high conduction current. Their robustness against overvoltage and overcurrent stresses is as important as their performance under normal operations. Such robustness is crucial for any power device, as they allow devices to temporarily survive the common faults in power systems, e.g., short circuit, excessive load, arc/ground faults, before the protection circuitry intervenes10. Avalanche is the desirable mechanism of power devices to withstand overvoltage stresses, as it allows them to accommodate high avalanche current (IAVA) at the avalanche breakdown voltage (BVAVA) and thus dissipate the excessive energy in circuits15. This fundamentally limits the robustness of UWBG power devices, of which Gallium oxide (Ga2O3) is an example16,17,18. Benefitting from its high critical electric field, controllable n-type do**, and the large-area wafer availability, Ga2O3 power devices are advancing fast towards applications19,20, Whereas, due to the flat valence band and strong self-trap** of holes, the reliable p-type do** in Ga2O3 is very challenging, although p-type Ga2O3 has been reported by some group21,22,23. As an alternative, heterojunctions between Ga2O3 and foreign p-type oxide, e.g., nickel oxide (NiO) or copper oxide24, have recently been deployed in the design of Ga2O3 bipolar power devices15. Despite excellent device performance, the viability of avalanche and surge robustness in such heterojunctions remains a fundamental knowledge gap. Meanwhile, the impact of band discontinuity on carrier transport is largely unexplored under the high electric field (E-field), high current density, and fast switching conditions.

This work fills this gap by demonstrating avalanche and surge robustness in NiO/Ga2O3 p-n heterojunctions through device innovations and circuit characterizations, whilst relevant carrier dynamics are also revealed through microscopic techniques and physics-based simulations. Large-area NiO/Ga2O3 p-n heterojunction diodes (HJDs) with advanced edge terminations are designed and fabricated, followed by the avalanche and surge circuit tests complying with industrial standards. Subsequently, the electron beam-induced current (EBIC) characterization and simulations reveal the carrier transport dynamics under critical avalanche and surge conditions. As a key enabler for surge robustness, the bipolar conductivity modulation is found to be dominantly in the NiO with a high hole concentration, while it is usually in the lightly-doped side in conventional homojunctions. This distinction allows NiO/Ga2O3 heterojunctions to simultaneously achieve a smaller reverse recovery and higher switching speed with robustness comparable or superior to that of conventional homojunction.

Results

NiO/Ga2O3 p-n heterojunction diode

For power devices, edge termination design is critical to control the E-field crowding, avoid premature breakdown, and access the device BVAVA. Here we employ an edge termination that combines small-angle beveled junction termination extension (JTE) and a high-k field plate. Figure 1a presents the three-dimensional schematic diagram of the large-area (3 mm × 3 mm) NiO/Ga2O3 p-n HJD fabricated on 2-inch free-standing Ga2O3 wafers. The p-type region consists of lightly- and heavily-doped NiO layers (i.e., p-NiO and p+-NiO). The p-NiO layer can reduce the leakage current and favor the JTE design. At the device edge, the p-NiO extension functions as a JTE, and the small beveled angle allows for a gradual decrease in charge density away from the active region, which continuously reduces the depletion curvature and surface E-field25. The high-k field plate conformally covers the NiO JTE and can further passivate the peak E-field.

Fig. 1: NiO/Ga2O3 p-n heterojunction power device.
figure 1

a Three-dimensional schematic of the NiO/Ga2O3 HJD, showing the double-layered NiO (a 300-nm-thick p-NiO and a 100-nm-thick p+-NiO) and a high permittivity BaTiO3 dielectric layer with 11° beveled-mesa termination. b STEM image of the termination region of the heterojunction in false color to highlight different layers. c High-resolution cross-section TEM image of the heterojunction interface. d Schematic energy band diagram of the HJD at zero bias. e Simulated in-plane E-field contour of devices with and without the BaTiO3 dielectric layer. f Frequency-dependent capacitance characteristics measured at different reverse bias voltages.

Full size image

The HJD fabrication starts with the deposition of NiO films on n-Ga2O3 drift layer via CMOS-compatible RF magnetron sputtering technique. The hole concentrations in NiO are modulated by tuning the gas flux ratios of Ar/O2 in the sputtering process, resulting in a hole concentration of 5.8 × 1017 cm−3 and 2.9 × 1019 cm−3 in p-NiO and p+-NiO layers, respectively. The beveled angle in NiO is implemented by adjusting the gap between the shadow mask and Ga2O3 wafer as well as the declination angle of the NiO target in the sputtering process, as detailed in Supplementary Section S1. Amorphous barium titanate (BaTiO3), a perovskite oxide with an ultrahigh dielectric constant, is deposited by RF sputtering between the anode metal and NiO to form the field plate. In addition to bare-die devices, some HJDs are sealed in TO-220 packages for circuit tests. More detailed fabrication and packaging process is described in Methods, Supplementary Section S1, and Supplementary Movie 1. Figure 1b shows the cross-sectional scanning transmittance electron microscopy (STEM) image of the edge termination, revealing a bevel angle of 11o. The high-resolution TEM image in Fig. 1c shows an atomically sharp interface of the NiO/Ga2O3 junction with excellent lattice alignments of the (111)-oriented NiO with (001) Ga2O3.

TCAD simulations are performed to investigate the heterojunction band structure and the device E-field management. The simulation models are detailed in Supplementary Section S4. As shown in Fig. 1d, at equilibrium, the NiO/Ga2O3 junction exhibits a type-II (staggered) band alignment with the conduction band and valence band offsets being 2.1 and 3.2 eV, respectively. Figure 1e shows the simulated E-field contours in the HJD with only the NiO JTE and full termination, both at a reverse bias of 1600 V. The high-k field plate shifts the peak E-field away from the junction edge and lowers the peak E-fields in Ga2O3 and NiO (from 6.61 MV/cm to 4.57 MV/cm and from 7.91 MV/cm to 2.62 MV/cm, respectively). As a result, a nearly uniform E-field is present at the NiO/Ga2O3 junction, enabling a uniform and robust avalanche.

Capacitance-voltage (C–V) characterizations are performed for the HJD at frequencies ranging from 1 kHz to 1 MHz, showing negligible frequency dispersion at various biases (Fig. 1f). This indicates the presence of minimal interface states at the heterojunction. The net donor concentration in the Ga2O3 drift layer and the built-in potential of the heterojunction are also extracted from the C–V characteristics to be 1.7 × 1016 cm−3 and 2.1 V, respectively (see Supplementary Section S2). From the built-in potential and band offsets, the barrier heights for electrons and holes are 4.2 and 5.3 eV, respectively. This suggests the electron injection could be more pronounced than hole injection at large forward biases.

Avalanche breakdown robustness

Avalanche breakdown is desirable for both power devices and power electronics systems. For devices, it allows for a non-destructive breakdown with a positive temperature coefficient of BVAVA12 and a smaller overvoltage margin as required for a certain voltage rating26. For systems, the concurrence of high IAVA and high BVAVA can dissipate the surge energy and prevent it from further circulating in the circuitry32,33, and largely unexplored under high E-field. As high IAVA hinges on efficient hole removal, the I. I.-produced holes in Ga2O3 are believed to be exempt from self-trap** under high E-field and drift with considerable mobility (μp). To estimate μp, we simulate the avalanche dynamics with μp of 10−4 and 1 cm2 V−1s−1 according to the low and high values theoretically predicted in the literature32,34, (μp is the low-field hole mobility, and field-dependent mobility model is detailed in Supplementary Section S4). Note that higher μp values, e.g., ~1.2 cm2/V s34 and 8~10 cm2/V s22,35, have been reported experimentally. Here we use two lower μp values in the simulation mainly to consider the worst scenario of avalanche, as a high μp can allow for a more efficient hole removal and thus supports a high avalanche current. At BVAVA, the drift velocity does not reach saturation under either μp values. Figure 2h, i shows the simulated contours of carrier concentrations, E-field and I. I. generation rate for the two μp, respectively. The low μp would induce serious hole accumulation and high E-field crowding at the heterojunction, making it unlikely to sustain a stable avalanche. These effects are eliminated for μp = 1 cm2 V−1s−1, rendering it a more reasonable μp to explain the avalanche in n-Ga2O3.

Surge current and reverse recovery characteristics

While avalanche represents the HJD’s robustness at reverse bias, surge current measures its capability to withstand forward overcurrent. Here, a 10-ms half-sinusoidal current pulse with an adjustable amplitude is employed for surge current characterization following the JEDEC standard36. Figure 3a shows the circuit schematic and the prototyped setup, with the circuit design detailed in Methods. Figure 3b, c shows the current and voltage waveforms in the surge current tests with increased amplitude. The HJD can withstand over 50 A surge current, under which condition the forward voltage approaches 14 V. Based on these time-resolved data, the surge current I–V locus are plotted in Fig. 3d for the HJD and a reference Ga2O3 Schottky barrier diode (SBD) fabricated on the same wafer. The surge current and voltage characteristics of the reference Ga2O3 SBD are shown in Supplementary Section S6. The locus of the HJD and SBD shows an anticlockwise and clockwise signature, respectively, which signifies negative and positive temperature coefficients (ηT) of the differential on-resistance (RON)12,

Methods

Epitaxial structure

The epitaxial structure was grown by hydride vapor phase epitaxy (HVPE) on a conductive Sn-doped (001) β-Ga2O3 substrate, consisting of a 10-μm Si-doped β-Ga2O3 drift layer with an electron concentration of 1.7 × 1016 cm−3. Based on the Hall measurements of the controlled NiO samples on semi-insulating substrates, hole mobilities corresponding to p-NiO (5.8 × 1017 cm−3) and p+-NiO (2.9 × 1019 cm−3) layers were determined to be 0.87 cm2/V s and 0.34 cm2/V s, respectively. Schematic of the processing steps is shown in Supplementary Section S1. The current-voltage characteristics of the p-NiO layer are shown in Supplementary Section S8.

Device fabrication

The device fabrication started with the substrate thinning from 640 μm to 150 μm by chemical mechanical polishing process, followed by substrate cleaning via ultrasonic treatment in acetone and soaking. Then, the Ga2O3 epi-wafers were annealed at 500 °C for 5 hours under the O2 ambient to partially compensate the donors in the epi-layer. The back-side Ohmic contact (cathode) was formed by the Ti/Au (20/80 nm) deposition through electron beam evaporation (EBE), followed by rapid thermal annealing at 500 °C for 1 min under N2 ambient. This annealing process has been reported to be able to effectively passivate near-surface defects in Ga2O3 epi-layer68. Note that the inter-diffusion of Sn from substrate and Si from epi-wafer is expected to be negligible at this annealing temperature69,70, Subsequently, by using an angled shadow mask, a 400-nm-thick double-layered NiO film with adjustable bevel angle was deposited on the Ga2O3 drift layer by RF magnetron sputtering technique at room temperature. During the sputtering process, the substrate was rotated at 4 rpm to enhance the film uniformity. The target was high-purity (99.99%) NiO ceramics. To alleviate the damage induced by sputtering plasma, the initial RF power was 50 W, and then increased to 150 W when the NiO thickness was above 20 nm. The distance between the target and the wafer was maintained at 13 cm. The growth pressure was 0.6 Pa in an Ar/O2 mixed ambient, and the flux ratios of Ar/O2 were tuned from 20:1 to 2:1 to modulate hole concentration in the double-layered NiO. A 300-nm-thick BaTiO3 was also deposited by RF magnetron sputtering at the same growth pressure of 0.6 Pa in an Ar/O2 mixed ambient with a flux ratio of 10:1, followed by annealing at 300 °C in oxygen ambient for 1 hour. The contact window was opened by a lift-off process, and Ni/Au (300/200 nm) metal stack was deposited by EBE to form the anode contact, producing an active area of 3 × 3 mm2.

Device package

The device was sealed in a TO-220 package for circuit testing. For the comparison of surge current characteristics, 9-mm2 Ni/β-Ga2O3 SBDs were also fabricated on the same wafer by identical processes except for the p-NiO deposition underneath the Schottky anode.

Device static electrical characterizations

The quasi-static forward/reverse I–V characterizations were performed by a B1505 power device analyzer. The pulse measurement mode in the B1505 analyzer was adopted to characterize the forward current above 1 A (Fig. 3e, f), while the high-resolution DC mode was used to measure the log-scale forward I–V characteristics of the HJD (Supplementary Section S7). The C–V characteristics were measured by using an E4980A precision LCR meter at room temperature.

Device circuit-level characterizations

The UIS, surge current, and reverse recovery characterizations were carried out by a customized circuit test platform. All test circuits and methods were formulated according to the Joint Electron Device Engineering Council (JEDEC) standards. Photographs of test circuits and experimental platforms are presented in Supplementary Section S3.

EBIC and TEM characterizations

EBIC measurement was carried out in an FEI Helios 600 NanoLab Dual-beam FIB system equipped with Kleindiek Nano Control NC40 nanomanipulators and low-current measurement units. The top- and bottom electrodes were contacted to the nanomanipulator and sample stage, respectively, allowing electrical current to flow and pass through a current amplifier. The electron beam direction is perpendicular to the surface of the junction, and the acceleration voltage and electron beam current were 15 kV and 0.17 nA, respectively. Line-scan measurement from the top electrode down to the Ga2O3 drift layer was performed to extract the profile of the EBIC current across the junction. Scanning TEM, bright-field high-resolution TEM, and energy dispersive X-ray (EDX) spectroscopy elemental map** were performed using an FEI Tecnai F-20 microscope (FEI TF-20), operated at an acceleration voltage of 200 kV.

Simulations

The Technology Computer-Aided Design (TCAD) device simulations were performed using the Silvaco TCAD device package. Additional details for the simulations are provided in Supplementary Section S4.