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Implementation of TCAM Controller Enabled CDMA Network on Chip Router for High-Speed 5G Communications

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Abstract

The 5G communications needs a high-speed data rate to satisfy the real-world communication applications. Further, the network on chip (NoC) plays the major role in real-time applications, which includes data communications, multi-processors and multi-controllers. However, existing NoC systems resulted in lower data rate with higher hardware resource utilization. Therefore, this article is focused on implementation of code division multiple access-NoC (CDMA-NoC router) using ternary content addressable memory (TCAM) buffer, Round Robin Arbiter (RRA) and XY-routing algorithm. Here, TCAM used to store the data generated across input and output ports. Further, TCAM also controls the read–write operations based on route requests. Then, RRA is used to allocate the priorities to the routes based on the traffic presented in the route. Finally, XY-routing algorithm transfers the data from source devices to destination devices through generated requests. Finally, the hardware-oriented simulations are conducted using **linx-ISE software platform and software-oriented simulations are conducted using Matlab-R2020a environment. The hardware-oriented simulations revealed that the proposed CDMA-NoC router resulted in superior area, delay, power performance as compared to state-of-art routers. The networking-oriented simulations also revealed that the proposed CDMA-NoC router resulted in superior networking performance in terms of data rates, energy efficiency, network capacity, and transmitted power for 250 number of users.

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References

  1. Mehmood F, et al. An efficient and cost effective application map** for network-on-chip using Andean condor algorithm. J Netw Comput Appl. 2022;200:103319.

    Article  Google Scholar 

  2. Chen Y-H, et al. A VLSI chip for the abnormal heart beat detection using convolutional neural network. Sensors. 2022;22(3):796.

    Article  MathSciNet  Google Scholar 

  3. Manzoor M, Mir RN. PAAD (Partially adaptive and deterministic routing): a deadlock free congestion aware hybrid routing for 2D mesh network-on-chips. Microproc Microsyst. 2022;92:104551.

    Article  Google Scholar 

  4. Yazdanpanah F, Mazayejani RA. A systematic analysis of power saving techniques for wireless network-on-chip architectures. J Syst Arch. 2022;126:102485.

    Article  Google Scholar 

  5. Biswas AK. Using pattern of on-off routers and links and router delays to protect network-on-chip intellectual property. ACM Trans Comput Syst (TOCS). 2022.

  6. Al-Azzwai WK, Al-Hilali AA, Jumma LF. Design and implementation 4x4 network on chip (NoC) using FPGA. Periodicals Eng Nat Sci (PEN). 2022;10(3):341–9.

    Article  Google Scholar 

  7. Seetharaman G, Pati D. Design and area performance energy consumption comparison of secured network-on-chip with PTP and bus interconnections. J Inst Eng India Ser B 2022: 1–13.

  8. **a Y, et al. Strict non-blocking four-port optical router for mesh photonic network-on-chip. J Semicond. 2022;43(9):092301.

    Article  MathSciNet  Google Scholar 

  9. Velangi R, Kerur SS. Hardware implementation and comparison of OE routing algorithm with extended XY routing algorithm for 2D mesh on network on chip. Micro-Electronics and Telecommunication Engineering. Springer, Singapore, 2022. 159–171.

  10. Kashi S, et al. A multi-application approach for synthesizing custom network-on-chips. J Supercomputing 2022: 1–23.

  11. Florida LM, Brilly Sangeetha S, Krishna Prasad K. Optimised meta-heuristic queuing model in vlsi physical design.

  12. Amin W, Hussain F, Anjum S. iHPSA: an improved bio-inspired hybrid optimization algorithm for task map** in Network on Chip. Microprocess Microsyst. 2022;90: 104493.

    Article  Google Scholar 

  13. Fan W, et al. Communication and performance evaluation of 3-ary n-cubes onto network-on-chips. Sci China Inf Sci. 2022;65(7):1–3.

    Article  MathSciNet  Google Scholar 

  14. Gupta R, et al. Securing on-chip interconnect against delay trojan using dynamic adaptive caging. Proceedings of the Great Lakes Symposium on VLSI 2022. 2022.

  15. Kaleem M, Isnin IFB. Interval based transaction record kee** mechanism for adaptive 3D network-on-chip routing.

  16. Imani MF, Abadal S, Del Hougne P. Metasurface-programmable wireless network-on-chip. Adv Sci. 2022;9:2201458.

    Article  Google Scholar 

  17. Thakkar IG, et al. Hardware security in emerging photonic network-on-chip architectures. Emerging computing: from devices to systems. Springer, Singapore, 2023. pp 291–313.

  18. Bhamidipati P, Karanth A. HREN: a hybrid reliable and energy-efficient network-on-chip architecture. IEEE Trans Emerg Top Comput. 2022;10(2):537–48.

    Google Scholar 

  19. Kunthara RG, et al. DAReS: deflection aware rerouting between subnetworks in bufferless on-chip networks. Proceedings of the Great Lakes Symposium on VLSI 2022. 2022.

  20. Firuzan A, Modarressi M, Reshadi M. Reconfigurable network-on-chip based Convolutional Neural Network accelerator. J Syst Arch. 2022;129:102567.

    Article  Google Scholar 

  21. Khan K, Pasricha S, Kim RG. RACE: a reinforcement learning framework for improved adaptive control of NoC channel buffers. Proceedings of the Great Lakes Symposium on VLSI 2022. 2022.

  22. Salehnamadi MR. A novel 3D mesh-based NoC architecture for performance improvement. Majlesi J Electric Eng 2022;16(2).

  23. Bhaskar AV. A detailed power analysis of network-on-chip. 2022 IEEE Delhi Section Conference (DELCON). IEEE, 2022.

  24. Bhaskar AV. Estimation of power consumption in a network-on-chip router. 2022 IEEE Delhi Section Conference (DELCON). IEEE, 2022.

  25. Singh S, Ravindra JV, Naik BR. Design and implementation of network‐on‐chip router using multi‐priority based iterative round‐robin matching with slip. Trans Emerg Telecommun Technol 2022: e4514.

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Correspondence to G. Renuka.

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This article is part of the topical collection “Advances in Computational Approaches for Image Processing, Wireless Networks, Cloud Applications and Network Security” guest edited by P. Raviraj, Maode Ma and Roopashree H R.

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Renuka, G., Anuradha, P., Reddy, P.L. et al. Implementation of TCAM Controller Enabled CDMA Network on Chip Router for High-Speed 5G Communications. SN COMPUT. SCI. 4, 740 (2023). https://doi.org/10.1007/s42979-023-02156-7

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