Abstract
The rapid advancement in nanoscale devices demands innovative gate dielectric materials to replace traditional Silicon dioxide. This paper investigates the electrical behavior and performance of a dual-gate FinFET employing different high-K gate dielectric materials (Silicon dioxide, Hafnium oxide, Titanium oxide) through ATLAS 2D simulation in 5 nm technology. We analyze how these high-K gate dielectric materials influence the device, focusing on performance enhancement. The study highlights various key performance parameters (\(I_{ON}\), \(I_{OFF}\), \(g_{m}\), \(g_{ds}\), \(R_{ON}\), TF, EV, \(V_{IL}\), \(V_{IH}\), \(NM_{L}\), \(NM_{H}\)) and reveals a significant performance improvement with \(\textrm{HfO}_2\) dielectric material in the proposed Dual-Gate FinFET. Achieving impressive performance parameters (\(I_{ON}\): 21.59 mA, \(I_{OFF}\): 21 \(\mu\)A, Maximum net Electric field: 1221290 V/cm, \(g_{m(max)}\): 0.05187 S, \(g_{ds(max)}\): 0.03462 S, \(R_{ON(max)}\): 25.93 k\(\Omega\), TFmax: 5.02, \(Gain_{max}\): 90.233, \(EV_{max}\): 67.532 V, \(V_{IL}\): 0.21 V, \(V_{IH}\): 0.4 V, \(NM_{L}\): 198 V, \(NM_{H}\): 600 V), this paper provides valuable insights for designing high-performance devices with \(\textrm{HfO}_2\) dielectric material.
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References
L. Artola, M. Gaillardin, G. Hubert, M. Raine, P. Paillet, Modeling single event transients in advanced devices and ICs. IEEE Trans. Nucl. Sci. 62(4), 1528–1539 (2015)
T. Dutta, S. Kumar, P. Rastogi, A. Agarwal, Y.S. Chauhan, Impact of channel thickness variation on bandstructure and source-to-drain tunneling in ultra-thin body III–V MOSFETs. IEEE J. Electron Devices Soc. 4(2), 66–71 (2016)
A.S. Roy, S.P. Mudanai, D. Basu, M.A. Stettler, Compact model for ultrathin low electron effective mass double gate MOSFET. IEEE Trans. Electron Devices 61(2), 308–313 (2014)
Z. Ren, R. Venugopal, S. Goasguen, S. Datta, M.S. Lundstrom, NanoMOS 2.5: a two-dimensional simulator for quantum transport in double-gate MOSFETs. IEEE Trans. Electron Devices 50(9), 1914–1925 (2003)
C. Yadav, J.P. Duarte, S. Khandelwal, A. Agarwal, C. Hu, Y.S. Chauhan, Capacitance modeling in III–V FinFETs. IEEE Trans. Electron Devices 62(11), 3892–3897 (2015)
M.D. Ganeriwala, C. Yadav, N.R. Mohapatra, S. Khandelwal, C. Hu, Y.S. Chauhan, Modeling of charge and quantum capacitance in low effective mass III–V FinFETs. IEEE J. Electron Devices Soc. 4(6), 396–401 (2016)
J.-J. Kim, K. Roy, Double gate-MOSFET subthreshold circuit for ultralow power applications. IEEE Trans. Electron Devices 51(9), 1468–1474 (2004)
S. **ong, J. Bokor, Sensitivity of double-gate and FinFETDevices to process variations. IEEE Trans. Electron Devices 50(11), 2255–2261 (2003)
A. Asenov, F. Adamu-Lema, X. Wang, S.M. Amoroso, Problems with the continuous do** TCAD simulations of decananometer CMOS transistors. IEEE Trans. Electron Devices 61(8), 2745–2751 (2014)
Q. Chen, E.M. Harrell, J.D. Meindl, A physical shortchannel threshold voltage model for undoped symmetric doublegate MOSFETs. IEEE Trans. Electron Devices 50(7), 1631–1637 (2003)
R. Rao, N. Dasgupta, A. Dasgupta, Study of random dopant fluctuation effects in FD-SOI MOSFET using analytical threshold voltage model. IEEE Trans. Device Mater. Rel. 10(2), 247–253 (2010)
J.-P. Colinge, Multiple-gate SOl MOSFETs. Solid-State Electron. 48(6), 897–905 (2004)
D. Tekleab, H.H. Tran, J.W. Sleight, and D. Chidambarrao “Silicon nanotube MOSFET,” U.S. Patent 20 120 217 468 A1 (2012)
N. Mohankumar, B. Syamal, C.K. Sarkar, Influence of channel and gate engineering on the analog and RF performance of DG MOSFETs. IEEE Trans. Electron Devices 57(4), 820–826 (2010)
A. Sarkar, A.K. Das, S. De, C.K. Sarkar, Effect of gate engineering in double-gate MOSFETs for analog/RF applications. Microelectron. J. 43(11), 873–882 (2012)
A. Mallik, A. Chattopadhyay, Tunnel field-effect transistors for analog/mixed-signal system-on-chip applications. IEEE Trans. Electron Devices 59(4), 888–894 (2012)
J. Widiez et al., Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance. IEEE Trans. Electron Devices 52(8), 1772–1779 (2005)
S. Chakraborty, A. Mallik, C.K. Sarkar, Subthreshold performance of dual-material gate CMOS devices and circuits for ultralow power analog/mixed-signal applications. IEEE Trans. Electron Devices 55(3), 827–832 (2008)
E.J. Pakaree, V.M. Srivastava, Realization with fabrication of double-gate MOSFET based differential amplifier. Microelectron. J. 91, 70–83 (2019)
M.V. Fischetti et al., Theoretical study of some physical aspects of electronic transport in nMOSFETs at the 10-nm gate-length. IEEE Trans. Electron Devices 54(9), 2116–2136 (2007)
S. Rashid, F. Bashir, F.A. Khanday, M.R. Beigh, F.A. Hussin, 2-D design of double gate Schottky tunnel MOSFET for high-performance use in analog/RF applications. IEEE Access 9, 80158–80169 (2021)
J. Yang, S. Jahdi, B. Stark, O. Alatise, J. Ortiz-Gonzalez, P. Mellor, Analysis of the 1st and 3rd quadrant transients of symmetrical and asymmetrical double-trench SiC power MOSFETs. IEEE Open J. Power Electron. 2, 265–276 (2021)
G.C. Patil, S. Qureshi, A novel \(\delta\)-doped partially insulated dopantsegregated Schottky barrier SOI MOSFET for analog/RF applications. Semicond. Sci. Technol. 26(8), 085002 (2011)
F. Bashir, S.A. Loan, M. Rafat, A.R.M. Alamoud, S.A. Abbasi, A high-performance source engineered charge plasma-based Schottky MOSFET on SOI. IEEE Trans. Electron Devices 62(10), 3357–3364 (2015)
F. Bashir, A.G. Alharbi, S.A. Loan, Electrostatically doped DSL Schottky barrier MOSFET on SOI for low power applications. IEEE J. Electron Devices Soc. 6, 19–25 (2018)
M. Fritze, C.L. Chen, S. Calawa, D. Yost, B. Wheeler, P. Wyatt, J. Larson, High-speed Schottky-barrier pMOSFET with fT / = 280 GHz. IEEE Electron Device Lett. 25(4), 220–222 (2004)
Y.K. Chin, K.-L. Pey, N. Singh, G.-Q. Lo, K.H. Tan, C.-Y. Ong, L.H. Tan, Dopant-segregated Schottky silicon-nanowire MOSFETs with gate-all-around channels. IEEE Electron Device Lett. 30(8), 843–845 (2009)
S. Rashid, F. Bashir, F.A. Khanday, M.R. Beigh, F.A. Hussin, 2-D design of double gate Schottky tunnel MOSFET for high-performance use in analog/RF applications. IEEE Access 9, 80158–80169 (2021)
S.K. Dargar, V.M. Srivastava, Design of double-gate tri-active layer channel based IGZO thin-film transistor for improved performance of ultra-low-power RFID rectifier. IEEE Access 8, 194652–194662 (2020)
S.S. Zaman, P. Kumar, M.P. Sarma, A. Ray and G. Trivedi, Design and simulation of SF-FinFET and SD-FinFET and their performance in analog, RF and digital applications. in 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), pp. 200–205 (2017)
K.P. Pradhan, S.K. Mohapatra, P.K. Sahu, D.K. Behera, Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET. Microelectron. J. 45(2), 144–151 (2014)
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Rao, M.V.G., Ramanjaneyulu, N., Pydi, B. et al. Enhancing Performance of Dual-Gate FinFET with High-K Gate Dielectric Materials in 5 nm Technology: A Simulation Study. Trans. Electr. Electron. Mater. 24, 557–569 (2023). https://doi.org/10.1007/s42341-023-00473-5
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DOI: https://doi.org/10.1007/s42341-023-00473-5