Log in

An efficient machine learning based CPU scheduler for heterogeneous multicore processors

  • Original Research
  • Published:
International Journal of Information Technology Aims and scope Submit manuscript

Abstract

While machine learning has excelled in various domains, its impact on computer architecture has been limited. Despite powerful, flexible multicore CPUs, efficient thread scheduling remains challenging due to map** overhead. This study introduces a novel approach that leverages machine learning to enhance CPU scheduling in heterogeneous multicore systems by develo** a map** methodology that improves system throughput. The proposed scheduling approach uses Long Short-Term Memory, Artificial Neural Networks, and Linear Regression to predict thread parameters and Instructions Per Cycle for threads running on different cores. The predicted values are then utilized to schedule threads using the map** that maximizes Instructions per Cycle count. The results demonstrate that the artificial neural network outperforms Linear Regression for predicting Instructions Per Cycle values. In addition, compared to traditional heterogeneous scheduling, the proposed machine learning-based scheduling approach enhances the performance of the heterogeneous system by about 1.2 times and increases throughput by 20%.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Subscribe and save

Springer+ Basic
EUR 32.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or Ebook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4

Similar content being viewed by others

Data availability

The data supporting this study's findings are available from the corresponding author upon reasonable request.

References

  1. Chen J, Manivannan M, Abduljabbar M, Pericàs M (2022) ERASE: Energy efficient task map** and resource management for work stealing runtimes. ACM Trans Archit Code Optim 19(2):1–29. https://doi.org/10.1145/3510422

    Article  Google Scholar 

  2. J. Chen, M. Manivannan, B. Goel, and M. Pericàs, JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency, in ACM International Conference Proceeding Series, Aug. 2023, pp. 828–838, https://doi.org/10.1145/3605573.3605586.

  3. Voudouris P, Stenström P, Pathan R (2022) Bounding the execution time of parallel applications on unrelated multiprocessors. Real-Time Syst 58(2):189–232. https://doi.org/10.1007/s11241-021-09375-2

    Article  Google Scholar 

  4. C. Bilbao, J. C. Saez, and M. Prieto-Matias, “Rapid Development of OS Support with PMCSched for Scheduling on Asymmetric Multicore Systems,” in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 13835 LNCS, 2023, pp. 184–196.

  5. C. V. Li, V. Petrucci, and D. Mosse, “Predicting thread profiles across core types via machine learning on heterogeneous multiprocessors,” in Brazilian Symposium on Computing System Engineering, SBESC, Nov. 2016, vol. 0, pp. 56–62, https://doi.org/10.1109/SBESC.2016.017.

  6. D. Nemirovsky, T. Arkose, N. Markovic, M. Nemirovsky, O. Unsal, and A. Cristal, “A Machine Learning Approach for Performance Prediction and Scheduling on Heterogeneous CPUs,” in Proceedings - 29th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017, Oct. 2017, pp. 121–128, https://doi.org/10.1109/SBAC-PAD.2017.23.

  7. Lin Z, Li C, Tian L, Zhang B (2022) A scheduling algorithm based on reinforcement learning for heterogeneous environments. Appl Soft Comput 130:109707. https://doi.org/10.1016/j.asoc.2022.109707

    Article  Google Scholar 

  8. D. Nemirovsky et al., “A deep learning mapper (DLM) for scheduling on heterogeneous systems,” in Communications in Computer and Information Science, vol. 796, 2018, pp. 3–20.

  9. E. Duesterwald, C. Caşcaval, and S. Dwarkadas, Characterizing and predicting program behavior and its variability, in Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, 2003, vol. 2003-Janua, pp. 220–231, https://doi.org/10.1109/PACT.2003.1238018.

  10. Sharma M, Kumar M, Samriya JK (2022) An optimistic approach for task scheduling in cloud computing. Int J Inf Technol 14(6):2951–2961. https://doi.org/10.1007/s41870-022-01045-1

    Article  Google Scholar 

  11. Neelakantan P, Yadav NS (2023) Proficient job scheduling in cloud computation using an optimized machine learning strategy. Int J Inf Technol 15(5):2409–2421. https://doi.org/10.1007/s41870-023-01278-8

    Article  Google Scholar 

  12. R. Kaur, V. Laxmi, and Balkrishan, Performance evaluation of task scheduling algorithms in virtual cloud environment to minimize makespan, Int. J. Inf. Technol., vol. 14, no. 1, pp. 79–93, Feb. 2022, https://doi.org/10.1007/s41870-021-00753-4.

  13. Yakubu IZ, Aliyu M, Musa ZA, Matinja ZI, Adamu IM (2021) Enhancing cloud performance using task scheduling strategy based on resource ranking and resource partitioning. Int J Inf Technol 13(2):759–766. https://doi.org/10.1007/s41870-020-00594-7

    Article  Google Scholar 

  14. Kumar PJ, Mini MG (2023) Machine learning based workload balancing scheme for minimizing stress migration induced aging in multicore processors. Int J Inf Technol 15(1):399–410. https://doi.org/10.1007/s41870-022-01105-6

    Article  Google Scholar 

  15. D. D. Penney and L. Chen, “A Survey of Machine Learning Applied to Computer Architecture Design,” CoRR, pp. 1–14, Sep. 2019, [Online]. http://arxiv.org/abs/1909.12373.

  16. Grammenos A, Charalambous T, Kalyvianaki E (2023) CPU scheduling in data centers using asynchronous finite-time distributed coordination mechanisms. IEEE Trans Netw Sci Eng 10(4):1880–1894. https://doi.org/10.1109/TNSE.2023.3236214

    Article  MathSciNet  Google Scholar 

  17. Y. Wen, Z. Wang, and M. F. P. O’Boyle, Smart multi-task scheduling for Open CL programs on CPU/GPU heterogeneous platforms, in 2014 21st International Conference on High Performance Computing, HiPC 2014, Dec. 2014, pp. 1–10, https://doi.org/10.1109/HiPC.2014.7116910.

  18. Stanisic L, Thibault S, Legrand A, Videau B, Méhaut JF (2015) Faithful performance prediction of a dynamic task-based runtime system for heterogeneous multi-core architectures. Concurr Comput Pract Exp 27(16):4075–4090. https://doi.org/10.1002/cpe.3555

    Article  Google Scholar 

  19. K. Chronaki, A. Rico, R. M. Badia, E. Ayguadé, J. Labarta, and M. Valero, Criticality-aware dynamic task scheduling for heterogeneous architectures, in Proceedings of the International Conference on Supercomputing, Jun. 2015, vol. 2015-June, pp. 329–338, https://doi.org/10.1145/2751205.2751235.

  20. Chronaki K et al (2017) Task scheduling techniques for asymmetric multi-core systems. IEEE Trans Parallel Distrib Syst 28(7):2074–2087. https://doi.org/10.1109/TPDS.2016.2633347

    Article  Google Scholar 

  21. Khalid YN, Aleem M, Ahmed U, Islam MA, Iqbal MA (2019) Troodon: A machine-learning based load-balancing application scheduler for CPU–GPU system. J Parallel Distrib Comput 132:79–94. https://doi.org/10.1016/j.jpdc.2019.05.015

    Article  Google Scholar 

  22. S. Parekh, S. Eggers, and H. Levy, Thread-sensitive scheduling for SMT processors, Univ. Washingt. Tech., pp. 1–18, 2000, [Online]. Available: http://scholar.google.com/scholar?hl=en&btnG=Search&q=intitle:Thread-Sensitive+Scheduling+for+SMT+Processors#0.

  23. D. Nemirovsky, Improving Heterogeneous System Efficiency : Architecture, Scheduling, and Machine Learning, Thesis, 2017.

  24. Li CV, Petrucci V, Mossé D (2017) Exploring machine learning for thread characterization on heterogeneous multiprocessors. Oper Syst Rev 51(1):113–123. https://doi.org/10.1145/3139645.3139664

    Article  Google Scholar 

  25. H. Sayadi, N. Patel, A. Sasan, and H. Homayoun, Machine learning-based approaches for energy-efficiency prediction and scheduling in composite cores architectures, Proc.—35th IEEE Int. Conf. Comput. Des. ICCD 2017, pp. 129–136, 2017, https://doi.org/10.1109/ICCD.2017.28.

  26. T. Helmy, S. Al-Azani, and O. Bin-Obaidellah, A machine learning-based approach to estimate the CPU-burst time for processes in the computational grids, Proc.—AIMS 2015, 3rd Int. Conf. Artif. Intell. Model. Simul., pp. 3–8, 2016, https://doi.org/10.1109/AIMS.2015.11.

  27. D. A. Shulga, A. A. Kapustin, A. A. Kozlov, A. A. Kozyrev, and M. M. Rovnyagin, The scheduling based on machine learning for heterogeneous CPU/GPU systems, in Proceedings of the 2016 IEEE North West Russia Section Young Researchers in Electrical and Electronic Engineering Conference, EIConRusNW 2016, Feb. 2016, pp. 345–348, https://doi.org/10.1109/EIConRusNW.2016.7448189.

Download references

Funding

Department of Science and Technology, Government of India, supported the research work through its FIST Program. Grant Number: SR/FST/ET-1/2019/445(C).

Author information

Authors and Affiliations

Authors

Contributions

All authors contributed to reviewing the literature, devising research hypotheses, conducting experiments, and writing and revising the manuscript.

Corresponding author

Correspondence to M. Tariq Banday.

Ethics declarations

Conflict of interest

The Authors declare that they do not have any conflict of interest.

Ethical approval

This article contains no studies performed by authors with human participants or animals.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Allaqband, S.F., Nazish, M., Allaqband, S.F. et al. An efficient machine learning based CPU scheduler for heterogeneous multicore processors. Int. j. inf. tecnol. (2024). https://doi.org/10.1007/s41870-024-01936-5

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s41870-024-01936-5

Keywords

Navigation