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Novel architecture of FFT implementation for 5G module using machine learning algorithms

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Abstract

This proposed work combines R2B, R4B, and R8B using signal delay feedback FFT architecture. R2B SDF FFT architecture has complex and large computations, and many stages are being used. To overcome this problem, Radix-4 and Radix-8 FFT are built to increase efficiency and decrease computational steps to incorporate in DUC and DDC filters and OFDM modules of 5G based modules. Signal delay feedback FFT architecture has stages that can have one clock per cycle. Each phase consists of a butterfly-type diagram in which the twiddle factors and rotators are used. In the proposed joined R2B, R4B, and R8B combined FFT, 5 phases of R2B FFT have been used with standard machine learning algorithms. When combined with complex R2B FFT, the combined R2B, R4B, and R8B FFT are less computational than the current technique. In the proposed method, the **linx tool is used to execute the introduced model.

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References

  • Dhillon HS, Mitra A (2008) A reduced-bit multiplication algorithm for digital arithmetic. Int J Electron Commun Eng 2(7):1442–1447

    MathSciNet  MATH  Google Scholar 

  • Hasan M, Chowdhury S, Faruqe O, Chakraborty A, Zaman HU, Islam S (2023) Wide word-length carry-select adder design using ripple carry and carry look-ahead method based hybrid 4-bit carry generator. Eng Rep. https://doi.org/10.1002/eng2.12721

    Article  Google Scholar 

  • Himanshu T, Srinivas MB (2005) VLSI implementation of RSA encryption system using ancient Indian vedic mathematics. VLSI Circuits Syst II 5837:888–892

    Article  Google Scholar 

  • Kerur SS, Prakash Narchi JCN, Kittur HM, Girish VA (2011) Implementation of vedic multiplier for digital signal processing, In: International conference on VLSI, Communication and instrumentation (ICVCI), pp 1–6

  • Matrassulova DK, Vitulyova YS, Konshin SV, Suleimenov IE (2023) Algebraic fields and rings as a digital signal processing tool. Indones J Electr Eng Comput Sci 29(1):206–216

    Google Scholar 

  • Meher PK, Mohanty BK, Patel SK, Ganguly S, Srikanthan T (2015) Efficient VLSI architecture for decimation-in-time fast Fourier transform of real-valued data. IEEE Trans Circuits Syst I: Reg Pap 62(12):2836–2845

    Article  MathSciNet  MATH  Google Scholar 

  • Mohanty BK, Meher PK (2018) Area–delay–energy efficient vlsi architecture for scalable in-place computation of fft on real data. IEEE Trans Circuits Syst I: Reg Pap 66(3):1042–1050

    Article  Google Scholar 

  • Parameswari D, Ananthalakshmi AV (2023) An efficient carry save multiplier for signal processing applications. Int J Comput Dig Syst 13(1):1–1

    Google Scholar 

  • Patel DK, Singh S (2021) VLSI architecture for combined R2B, R4B and R8B FFT using SDF and modified CSLA, In: 2021 international conference on computer communication and informatics (ICCCI), pp 1–5. IEEE

  • Qureshi F, Takala J, Volkova A, Hilaire T (2017) Multiplierless unified architecture for mixed radix-2/3/4 FFTs, In: 2017 25th European signal processing conference (EUSIPCO), pp 1334–1338. IEEE

  • Vaidya S, Dandekar D (2010) Delay-power performance comparison of multipliers in VLSI circuit design. Int J Comput Netw Commun 2(4):47–56

    Google Scholar 

  • Ykuntam YD, Penumutchi B, Gubbala S (2023) Design of speed and area efficient non linear carry select adder (NLCSLA) architecture using XOR less adder module, In: Advances in signal processing, embedded systems and IoT: Proceedings of seventh ICMEET-2022, pp 81–91. Singapore: Springer Nature Singapore

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All authors certify that they have no affiliations with or involvement in any organization or entity with any financial interest or non-financial interest in the subject matter or materials discussed in this manuscript. The authors have no financial or proprietary interests in any material discussed in this article.

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Correspondence to K. Narsimha Reddy.

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Malladhi, N., Reddy, K.N. & Vallabhuni, R.R. Novel architecture of FFT implementation for 5G module using machine learning algorithms. Int J Syst Assur Eng Manag 14, 2387–2394 (2023). https://doi.org/10.1007/s13198-023-02087-9

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  • DOI: https://doi.org/10.1007/s13198-023-02087-9

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