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Investigation of interface trap charges and temperature variation in heterostacked-TFET

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Abstract

This paper analyzes the reliability issues of the Heterostacked-TFET (HS-TFET) in detail. The investigation of the device reliability is carried out by examining the effect of interface trap charges (ITCs) and the temperature affectability of the HS-TFET on various analog parameters and RF FOMs. The analysis is performed at different interface trap charge densities and polarities. The presence of interface traps at the stackedsource/channel junction and the oxide/silicon interface alters the performance of the device significantly. A positive trap charge density of 3 × 1013 cm−2 degrades the current switching ratio tremendously from an order of 1010–104. The off-state current of the device deteriorates excessively at high temperatures. However, the results establish that the HS-TFET is insusceptible to the acceptor interface trap charge as compared to the donor interface trap charge for temperature variation. A high-k gate dielectric of Aluminum oxide (Al2O3) is considered and compared with Hafnium oxide (HfO2) and it is found that Al2O3 gate oxide has a better immunity to the ITC variation.

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Acknowledgements

This publication is an outcome of the R&D work undertaken in the project under the Visvesvaraya PhD Scheme of Ministry of Electronics & Information Technology, Government of India, being implemented by Digital India Corporation (formerly Media Lab Asia).

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  1. Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Silchar, Assam, 788010, India

    K. Vanlalawmpuia & Brinda Bhowmick

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  1. K. Vanlalawmpuia
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  2. Brinda Bhowmick
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Correspondence to K. Vanlalawmpuia.

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Vanlalawmpuia, K., Bhowmick, B. Investigation of interface trap charges and temperature variation in heterostacked-TFET. Indian J Phys 95, 1697–1708 (2021). https://doi.org/10.1007/s12648-020-01834-z

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  • DOI: https://doi.org/10.1007/s12648-020-01834-z

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