Abstract
Deep trench LDMOS is widely used in high-voltage level power devices. This paper proposes and optimizes a deep trench super-junction LDMOS with triangular charge compensation layer (TCCL DT SJ LDMOS), which solves the problem of charge imbalance in the super-junction region due to the Silicon-Insulator-Silicon (SIS) capacitance at both ends of the trench and improves the Breakdown Voltage (BV) of the device. This structure also helps to deplete the drift region at the bottom of the deep trench by adding P-buffer under the N-Pillars, which improves the do** concentration and reduces the specific on-resistance of the device. The simulation results show that compared with the Con. DT SJ LDMOS, the BV of the TCCL DT SJ LDMOS has been increased from 498V to 730V, and the power figure of merit (FOM) has increased by 12.8 MW / cm2(FOM = BV2 / Ron, sp).
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This work was supported by Scientific Research Fund of Hunan Provincial Education Department (No. 19K001).
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Wu, L., Ding, Q. & Chen, J. Improved Deep Trench Super-junction LDMOS Breakdown Voltage By Shielded Silicon-Insulator-Silicon Capacitor. Silicon 13, 3441–3446 (2021). https://doi.org/10.1007/s12633-020-00771-0
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DOI: https://doi.org/10.1007/s12633-020-00771-0