Abstract
Lateral Double Diffused Metal Oxide Field Effect Transistor (LDMOS) are widely used in power applications for the high breakdown voltage. However, the device may have high on-resistance. So, the challenge for achieving high breakdown voltage and small on-resistance is important. In this paper, a new structure is proposed to enhance the conventional LDMOS performance. In this case, a U-shape P silicon layer is considered in bottom of the drift region and under the gate. The P layer has higher do** density than the drift region which is different from the channel and source/drain. This difference creates some new peaks in the electric field profile decreasing the main peaks. Therefore, the breakdown voltage significantly increases. The on-resistance is reduced when the do** density increases. The higher do** density of P layer than drift region reduces the on-resistance. The paper is simulated using two dimensional ATLAS simulator and is compared to the conventional one. The simulation results show that the proposed structure performance is acceptable in case of electric voltage, breakdown voltage, on-resistance and switching characteristics.
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Zareiee, M. A New Structure for Lateral Double Diffused MOSFET to Control the Breakdown Voltage and the On-Resistance. Silicon 11, 3011–3019 (2019). https://doi.org/10.1007/s12633-019-0092-5
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DOI: https://doi.org/10.1007/s12633-019-0092-5