Abstract
Hardware/software (HW/SW) partitioning is one of the key processes in an embedded system. It is used to determine which system components are assigned to hardware and which are processed by software. In contrast with previous research that focuses on develo** efficient heuristic, we focus on the pre-process of the task graph before the HW/SW partitioning in this paper, that is, enumerating all the sub-graphs that meet the requirements. Experimental results showed that the original graph can be reduced to 67% in the worst-case scenario and 58% in the best-case scenario. In conclusion, the reduced task graph saved hardware area while improving partitioning speed and accuracy.
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References
Wu Jigang, Thambipillai S. Low-complex dynamic programming algorithm for hardware/software partitioning[J]. Information Processing Letters, 2006, 98(2): 41–46.
Silva L, Sampaio A, Barros. A constructive approach to hardware/software partitioning[J]. Fromal Methods in System Design, 2004, 24(1): 45–90.
Wu Jigang, Thambipillai S, Tao Jiao. Algorithmic aspects for functional partitioning and scheduling in hardware/software co-design[J]. Design Automation for Embedded Systems, 2008, 12(4): 345–375.
Kuang S R, Chen C Y, Liao R Z. Partitioning and pipelined scheduling of embedded system using integer linear programming [EB/OL]. [2010-11-10]. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=01524246.
Eles P, Peng Z, Kuchcinski K, et al. System level hardware/software partitioning based on simulated annealing and tabu search[J]. Des Autom Embedded Syst, 1997, 2(1): 5–32.
Quan Gang, Hu **aobo, Greenwood G. Preference-driven hierarchical hardware/software partitioning [EB/OL]. [2010-11-05]. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=08611.
Tong Qiaoling, Zou Xuecheng, Zhang Qiao, et al. The hardware/software partitioning in embedded system by improved particle swarm optimization algorithm [EB/OL]. [2010-10-15]. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=690722.
Gomes da Silva C, Clímaco J, Rui Figueira J. Core problems in bi-criteria {0, 1}-knapsack problems[J]. Computers & Operations Research 35, 2008: 2292–2306.
Hassan Y, Ashraf S. A high performance algorithm for scheduling and hardware-software partitioning on MPSoCs [C]// Design & Technology of Integrated Systems in Nanoscal Era. Cairo: IEEE Press, 2009: 71–76.
Henkel J, Ernst R. An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques[J]. IEEE Trans Very Large Scale Integr VLSI Syst, 2001, 9(2): 273–289.
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Foundation item: Supported by the National Natural Science Foundation of China (60970016, 61173032)
Biography: LI Hui, female, Master candidate, research direction: high-performance algorithms.
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Li, H., Liu, W., Wu, J. et al. Task graph reduction algorithm for hardware/software partitioning. Wuhan Univ. J. Nat. Sci. 17, 126–130 (2012). https://doi.org/10.1007/s11859-012-0816-5
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DOI: https://doi.org/10.1007/s11859-012-0816-5