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Influence of Structural Parameters on the Behavior of an Asymmetric Linearly Graded Workfunction Trapezoidal Gate SOI MOSFET

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Abstract

This paper presents a dual metal trapezoidal recessed channel metal oxide semiconductor field effect transistor (MOSFET) embedded with asymmetric stack gate with linearly graded metal work-function technique to improve the carrier transport efficiency and device switching performance. The analytical model for the proposed asymmetric-linearly graded trapezoidal gate (ASY–LGTG) silicon on insulator (SOI) MOSFET has been developed considering parabolic approximation of 2-D Poisson’s equation. The threshold voltage of the device is extracted using minimum surface potential. The simulation work has been carried out using a Silvaco TCAD tool to validate the results of the analytical model. This grooved structure exhibits the corner effect, which plays a dynamic role in the improvement of the device performance. However, the impact of the corner effect can be controlled by the groove corner angle and do** concentration. We have also investigated the impact of different structural parameters such as negative junction depth (NJD), corner angle, substrate do** and stack gate features (upper oxide permittivity and oxide thickness ratio) on the performance of minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage and device switching characteristics.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Institute of Technical Education and Research, Siksha ‘O’ Anusandhan Deemed to be University, Khandagiri, Bhubaneswar, India

    Sikha Mishra

  2. Department of Electronics and Telecommunication Engineering, National Institute of Technology Raipur, Chhattisgarh, India

    Guru Prasad Mishra

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  1. Sikha Mishra
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  2. Guru Prasad Mishra
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Correspondence to Guru Prasad Mishra.

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Mishra, S., Mishra, G.P. Influence of Structural Parameters on the Behavior of an Asymmetric Linearly Graded Workfunction Trapezoidal Gate SOI MOSFET. J. Electron. Mater. 48, 6607–6616 (2019). https://doi.org/10.1007/s11664-019-07465-3

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