Abstract
In this work, we design and simulate carbon nanotube field effect transistor (CNTFET) based open-loop and dynamic comparators and compared the performance with complementary metal oxide semiconductor (CMOS) based open loop and dynamic comparators. Four types of comparators have been designed; a two-stage comparators, a push–pull output comparators, dynamic comparators and double-tail dynamic comparator (DTDC), employing 32 nm technology node using CNTFETs and the conventional MOSFETs. A comparative analysis of key performance measuring parameters such as output voltage, rise time, fall time, duty cycle, average power and slew rate and area etc. have been done. The simulation studies have shown that the CNTFET based comparators consumes lesser power by 3 orders, results in higher speed and gives output close to their supply rails in comparison to CMOS based comparators. Further, effects of variation in temperature on frequency and power have been thoroughly studied. Simulation results show that CNTFET based comparators gives insensitive behavior for variation in temperature. All the proposed circuits are fully integrable because of the use of active components in the circuits.
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig1_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig2_HTML.jpg)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig3_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig4_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig5_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig6_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig7_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig8_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig9_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig10_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig11_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig12_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig13_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig14_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-022-02119-7/MediaObjects/10470_2022_2119_Fig15_HTML.png)
Similar content being viewed by others
Data availability
The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.
References
Danesh, S., Hurwitz, J., Findlater, K., Renshaw, D., & Henderson, R. (2013). A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit highly time-interleaved counter ADC with low power comparator design. IEEE Journal of Solid-State Circuits, 48, 733–748.
Gupta, R., Gupta, R., & Sharma, S. (2017). Design of high speed and low power 4-bit comparator using FGMOS. AEU—International Journal of Electronics and Communications, 76, 125–131.
Khorami, A., & Sharifkhani, M. (2016). High-speed low-power comparator for analog to digital converters. AEU International Journal of Electronics and Communications, 70, 886–894.
De La Fuente-Cortes, G., Espinosa Flores-Verdad, G., Gonzalez-Diaz, V. R., & Diaz-Mendez, A. (2017). A new CMOS comparator robust to process and temperature variations for SAR ADC converters. Analog Integrated Circuits Signal Process, 90, 301–308.
Goll, B., & Zimmermann, H. (2009). A comparator with reduced delay time in 65-Nm CMOS for supply voltages down to 065 V. IEEE Transactions on Circuits and Systems II: Express Briefs, 56, 810–814.
Khatak, A., Manoj, K., & Sanjeev, D. (2018). "An improved cmos design op-amp comparator with gain boosting technique for data converter circuits. Journal of Low Power Electronics and Applications, 8(4), 33.
Maji, K. B., Kar, R., Mandal, D., & Ghoshal, S. P. (2016). An evolutionary approach based design automation of low power CMOS two-stage comparator and folded cascode OTA. AEU-International Journal of Electronics and Communications, 70(4), 398–408.
Kale, S., & Gamad, R. S. (2010). Design of a CMOS comparator for low power and high speed. Internationl Journal of Electronic Engineering Research, 2(1), 29–34.
Gowrisankar, P. A., & Udhayakumar, K. (2014). A novel carbon nanotube field effect transistor based analog signal processing circuits for low-power communication systems. Emerging Trends in Computing and Communication (pp. 329–340). Springer.
Bendre, V. S., Kureshi, A. K., & Waykole, S. (2018). Design of analog signal processing applications using carbon nanotube field effect transistor-based low-power folded cascode operational amplifier. Journal of Nanotechnology. https://doi.org/10.1155/2018/2301421
Dharmendra, B. M., Arun, B., & Nandurbarkar, B. (2014). Study and Implementation of comparator in CMOS 50nm Technology. International Journal Of research and engineering Technology (IJRET), 3(2), 252–255.
Jeon, H. J., & Kim, Y.-B. (2012). A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator. Analog Integrated Circuits and Signal Processing, 70(3), 337–346.
Huang, S., Diao, S., & Lin, F. (2016). An energy-efficient high-speed CMOS hybrid comparator with reduced delay time in 40-nm CMOS process. Analog Integrated Circuits and Signal Processing, 89(1), 231–238.
Khorami, A., & Sharifkhani, M. (2016). High-speed low-power comparator for analog to digital converters. AEU-International Journal of Electronics and Communications, 70(7), 886–894.
Zhang, X., Li, S., Siferd, R., & Ren, S. (2020). High-sensitivity high-speed dynamic comparator with parallel input clocked switches. AEU-International Journal of Electronics and Communications, 122, 153236.
Mahmoodian, H., Dolatshahi, M., Zanjani, S. M., & Honarvar, M. A. (2022). An energy-efficient dynamic comparator in carbon nanotube field effect transistor technology for successive approximation register ADC applications. IET Circuits, Devices & Systems. https://doi.org/10.1049/cds2.12112
Dubey, A. K., & Nagaria, R. K. (2019). Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage. Analog Integrated Circuits and Signal Processing, 101(2), 307–317.
Savani, V., & Devashrayee, N. M. (2017). Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator. Analog Integrated Circuits and Signal Processing, 93(2), 287–298.
Dubey, A. K., & Nagaria, R. K. (2018). Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load. Microelectronics Journal, 78, 1–10.
Rahmani, S., & Ghaznavi-Ghoushchi, M. B. (2017). Design and analysis of a high speed double-tail comparator with isomorphic latch-preamplifier pairs and tail bootstrap**. Analog Integrated Circuits and Signal Processing, 93(3), 507–521.
Bryant, J. (2006). Using op amps as comparators. Analog Devices, Application note AN-849.
Iwai, H. (2006). "Recent status on nano CMOS and future direction." In 2006 International workshop on nano CMOS, IEEE (pp. 1–5).
Ho, R., Lau, C., Hills, G., & Shulaker, M. M. (2019). Carbon nanotube CMOS analog circuitry. IEEE Transactions on nanotechnology, 18, 845–848.
Deng, J., & Wong, H.-P. (2007). A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part II: Full device model and circuit performance benchmarking. IEEE Transactions on Electron Devices, 54(12), 3195–3205. https://doi.org/10.1109/TED.2007.909043
Stanford University (2008) CNFET model website, Online Available: https://nano.stanford.edu/model.php.
Iijima, S. (1991). Helical microtubules of graphitic carbon. Nature, 354, 56–58.
Taczak, M.D. (2007) Controlling the structure and properties of carbon nanotubes.
Nizamuddin, M., Loan, S. A., Alamoud, A. M., & Alharbi, A. G. (2017). Design, simulation and the comparative analysis of CNTFET based mulistage amplifier. Journal of Nanoelectronics and Optoelectronics, 12, 1045–1055.
Nizamuddin, M., Loan, S. A., Alamoud, A. R., & Abbassi, S. A. (2015). Design, simulation and comparative analysis of CNT based cascode operational transconductance amplifiers. Nanotechnology, 26(39), 39520.
Scoville, C., Robin C., Jason H., Omar F., & Archie R. (1991). Carbon Nanotubes. Notes Lect (pp. 1–11).
Akhoon, M.S., Alharbi, A.G., Bhat, M.A., Suandi, S.A., Ashraf, J., Loan, S.A. (2021). "Design and simulation of carbon nanotube based current source load differential amplifier." In: 2021 international conference on microelectronics (ICM). IEEE, pp. 140–143.
Allen, P. E., & Holberg, D. R. (2002). CMOS analog circuit design. Oxford University Press.
Nizamuddin, M., Loan, S. A., Alamoud, A. R., & Abbassi, S. A. (2015). "Design, simulation and comparative analysis of CNT based cascode operational transconductance amplifiers. Nanotechnology, 26(39), 39520.
Han, Z., & Alberto, F. (2011). Thermal conductivity of carbon nanotubes and their polymer nanocomposites: A review. Progress in Polymer Science, 36(7), 914–944.
Usmani, F. A., & Hasan, M. (2010). Carbon nanotube field effect transistors for high performance analog applications: An optimum design approach. Microelectronics Journal, 41(7), 395–402.
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
About this article
Cite this article
Jogad, S., Akhoon, M.S. & Loan, S.A. CNTFET based comparators: design, simulation and comparative analysis. Analog Integr Circ Sig Process 114, 265–273 (2023). https://doi.org/10.1007/s10470-022-02119-7
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-022-02119-7